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| Under development This document is under development and its contents are subject to change M16C/6N Group (M16C/6N5) Renesas MCU REJ03B0004-0240 Rev.2.40 Aug 25, 2006 1. Overview The M16C/6N Group (M16C/6N5) of MCUs are built using the high-performance silicon gate CMOS process using the M16C/60 Series CPU core and are packaged in 100-pin plastic molded QFP and LQFP. These MCUs operate using sophisticated instructions featuring a high level of instruction efficiency. With 1 Mbyte of address space, they are capable of executing instructions at high speed. Being equipped with one CAN (Controller Area Network) module in the M16C/6N Group (M16C/6N5), the MCU is suited to drive automotive and industrial control systems. The CAN module complies with the 2.0B specification. In addition, this MCU contains a multiplier and DMAC which combined with fast instruction processing capability, makes it suitable for control of various OA, communication, and industrial equipment which requires high-speed arithmetic/ logic operations. 1.1 Applications * Automotive, industrial control systems and other automobile, other (T/V-ver. product) * Car audio and industrial control systems, other (Normal-ver. product) Specifications written in this manual are believed to be accurate, but are not guaranteed to be entirely free of error. Specifications in this manual may be changed for functional or performance improvements. Please make sure your manual is the latest edition. Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 1 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 1. Overview 1.2 Performance Overview Table 1.1 lists the Functions and Specifications for M16C/6N Group (M16C/6N5). Table 1.1 Functions and Specifications for M16C/6N Group (M16C/6N5) Specification Item Normal-ver. T/V-ver. CPU Number of fundamental 91 instructions instructions Minimum instruction 41.7 ns (f(BCLK) = 24 MHz, 50.0 ns (f(BCLK) = 20 MHz, execution time 1/1 prescaler, without software wait) 1/1 prescaler, without software wait) Operating mode Single-chip, memory expansion, and microprocessor modes Address space 1 Mbyte Memory capacity Refer to Table 1.2 Product Information Peripheral Ports Input/Output: 87 pins, Input: 1 pin Function Multifunction timers Timer A: 16 bits 5 channels Timer B: 16 bits 6 channels Three-phase motor control circuit Serial interfaces 3 channels Clock synchronous, UART, I2C-bus (1), IEBus (2) 1 channel Clock synchronous A/D converter 10-bit A/D converter: 1 circuit, 26 channels D/A converter 8 bits 2 channels DMAC 2 channels CRC calculation circuit CRC-CCITT CAN module 1 channel with 2.0B specification Watchdog timer 15 bits 1 channel (with prescaler) Interrupts Internal: 29 sources, External: 9 sources Software: 4 sources, Priority levels: 7 levels Clock generation circuits 4 circuits * Main clock oscillation circuit (*) * Sub clock oscillation circuit (*) * On-chip oscillator * PLL frequency synthesizer (*) Equipped with on-chip feedback resistor Oscillation-stopped detector Main clock oscillation stop and re-oscillation detection function Electrical Supply voltage VCC = 3.0 to 5.5 V (f(BCLK) = 24 MHz, VCC = 4.2 to 5.5 V (f(BCLK) = 20 MHz, Characteristics 1/1 prescaler, without software wait) 1/1 prescaler, without software wait) Consumption Mask ROM 18 mA (f(BCLK) = 24 MHz, 16 mA (f(BCLK) = 20 MHz, current PLL operation, no division) PLL operation, no division) Flash memory 20 mA (f(BCLK) = 24 MHz, 18 mA (f(BCLK) = 20 MHz, PLL operation, no division) PLL operation, no division) Mask ROM 3 A (f(BCLK) = 32 kHz, Wait mode, Oscillation capacity Low) Flash memory 0.8 A (Stop mode, Topr = 25C) Flash Memory Programming and erasure voltage 3.0 0.3 V or 5.0 0.5 V 5.0 0.5 V Version Programming and erasure endurance 100 times I/O I/O withstand voltage 5.0 V Characteristics Output current 5 mA Operating Ambient Temperature -40 to 85C T version: -40 to 85C V version: -40 to 125C (option) Device Configuration CMOS high-performance silicon gate Package 100-pin molded-plastic QFP, LQFP NOTES: 1. I2C-bus is a trademark of Koninklijke Philips Electronics N.V. 2. IEBus is a trademark of NEC Electronics Corporation. option: All options are on request basis. Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 2 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 1. Overview 1.3 Block Diagram Figure 1.1 shows a Block Diagram. 8 8 8 8 8 8 8 Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Port P6 Port P7 Internal peripheral functions Timer (16 bits) Output (timer A): 5 Input (timer B): 6 Three-phase motor control circuit Watchdog timer (15 bits) A/D converter (10 bits 8 channels Expandable up to 26 channels) UART or Clock synchronous serial I/O (3 channels) CRC calculation circuit (CCITT) (Polynomial: X16+X12+X5+1) System clock generation circuit XIN-XOUT XCIN-XCOUT PLL frequency synthesizer On-chip oscillator Clock synchronous serial I/O (8 bits 1 channel) CAN module (1 channel) 8 Port P8 Port P8_5 7 M16C/60 Series CPU core R0H R1H R0L R1L R2 R3 A0 A1 FB SB USP ISP Memory ROM (1) RAM (2) Port P9 DMAC (2 channels) 8 INTB Port P10 D/A converter (8 bits 2 channels) PC FLG Multiplier 8 NOTES: 1: ROM size depends on MCU type. 2: RAM size depends on MCU type. Figure 1.1 Block Diagram Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 3 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 1. Overview 1.4 Product Information Table 1.2 lists the Product Information and Figure 1.2 shows the Type Number, Memory Size, and Packages. Table 1.2 Product Information As of Aug. 2006 Type No. ROM Capacity RAM Capacity Package Type (2) Remarks M306N5FCFP 128 K + 4 Kbytes 5 Kbytes PRQP0100JB-A Flash Normal-ver. M306N5FCGP PLQP0100KB-A memory M306N5FCTFP PRQP0100JB-A version (1) T-ver. M306N5FCTGP PLQP0100KB-A M306N5FCVFP PRQP0100JB-A V-ver. M306N5FCVGP PLQP0100KB-A M306N5MC-XXXGP 128 Kbytes 5 Kbytes PLQP0100KB-A Mask Normal-ver. M306N5MCT-XXXFP PRQP0100JB-A ROM T-ver. M306N5MCT-XXXGP PLQP0100KB-A version M306N5MCV-XXXFP PRQP0100JB-A V-ver. M306N5MCV-XXXGP (D) PLQP0100KB-A (D): Under development NOTES: 1. Data flash memory provides an additional 4 Kbytes of ROM capacity (block A). 2. The correspondence between new and old package types is as follows. PRQP0100JB-A: 100P6S-A PLQP0100KB-A: 100P6Q-A Type No. M30 6N 5 M C T - XXX FP Package type: FP : Package PRQP0100JB-A (100P6S-A) GP: Package PLQP0100KB-A (100P6Q-A) ROM No. Omitted on flash memory version Characteristics (no) : Normal-ver. T : T-ver. (Automotive 85C version) V : V-ver. (Automotive 125C version) ROM capacity: C : 128 Kbytes Memory type: M: Mask ROM version F : Flash memory version Shows the number of CAN module, pin count, etc. 6N Group M16C Family Figure 1.2 Type Number, Memory Size, and Package Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 4 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 1. Overview 1.5 Pin Assignments Figures 1.3 and 1.4 show the Pin Assignment (Top View). Tables 1.3 and 1.4 list the List of Pin Names. P0_7/AN0_7/D7 P0_6/AN0_6/D6 P0_5/AN0_5/D5 P0_4/AN0_4/D4 P0_3/AN0_3/D3 P0_2/AN0_2/D2 P0_1/AN0_1/D1 P0_0/AN0_0/D0 P10_7/AN7/KI3 P10_6/AN6/KI2 P10_5/AN5/KI1 P10_4/AN4/KI0 P10_3/AN3 P10_2/AN2 P10_1/AN1 AVSS P10_0/AN0 VREF AVCC P9_7/ADTRG 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P1_0/D8 P1_1/D9 P1_2/D10 P1_3/D11 P1_4/D12 P1_5/D13/INT3 P1_6/D14/INT4 P1_7/D15/INT5 P2_0/AN2_0/A0(/D0/-) P2_1/AN2_1/A1(/D1/D0) P2_2/AN2_2/A2(/D2/D1) P2_3/AN2_3/A3(/D3/D2) P2_4/AN2_4/A4(/D4/D3) P2_5/AN2_5/A5(/D5/D4) P2_6/AN2_6/A6(/D6/D5) P2_7/AN2_7/A7(/D7/D6) VSS P3_0/A8(/-/D7) VCC2 P3_1/A9 P3_2/A10 P3_3/A11 P3_4/A12 P3_5/A13 P3_6/A14 P3_7/A15 P4_0/A16 P4_1/A17 P4_2/A18 P4_3/A19 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 M16C/6N Group (M16C/6N5) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 P4_4/CS0 P4_5/CS1 P4_6/CS2 P4_7/CS3 P5_0/WRL/WR P5_1/WRH/BHE P5_2/RD P5_3/BCLK P5_4/HLDA P5_5/HOLD P5_6/ALE P5_7/RDY/CLKOUT P6_0/CTS0/RTS0 P6_1/CLK0 P6_2/RXD0/SCL0 P6_3/TXD0/SDA0 P6_4/CTS1/RTS1/CTS0/CLKS1 P6_5/CLK1 P6_6/RXD1/SCL1 P6_7/TXD1/SDA1 NOTE: 1. P7_1 and P9_1 are N channel open-drain pins. Figure 1.3 Pin Assignments (Top View) (1) Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 5 of 84 P9_6/ANEX1/CTX0 P9_5/ANEX0/CRX0 P9_4/DA1/TB4IN P9_3/DA0/TB3IN P9_2/TB2IN/SOUT3 (1) P9_1/TB1IN/SIN3 P9_0/TB0IN/CLK3 BYTE CNVSS P8_7/XCIN P8_6/XCOUT RESET XOUT VSS XIN VCC1 P8_5/NMI P8_4/INT2/ZP P8_3/INT1 P8_2/INT0 P8_1/TA4IN/U P8_0/TA4OUT/U P7_7/TA3IN P7_6/TA3OUT P7_5/TA2IN/W P7_4/TA2OUT/W P7_3/CTS2/RTS2/TA1IN/V P7_2/CLK2/TA1OUT/V (1) P7_1/RXD2/SCL2/TA0IN/TB5IN P7_0/TXD2/SDA2/TA0OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Package: PRQP0100JB-A (100P6S-A) Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 1. Overview P1_2/D10 P1_1/D9 P1_0/D8 P0_7/AN0_7/D7 P0_6/AN0_6/D6 P0_5/AN0_5/D5 P0_4/AN0_4/D4 P0_3/AN0_3/D3 P0_2/AN0_2/D2 P0_1/AN0_1/D1 P0_0/AN0_0/D0 P10_7/AN7/KI3 P10_6/AN6/KI2 P10_5/AN5/KI1 P10_4/AN4/KI0 P10_3/AN3 P10_2/AN2 P10_1/AN1 AVSS P10_0/AN0 VREF AVCC P9_7/ADTRG P9_6/ANEX1/CTX0 P9_5/ANEX0/CRX0 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 P1_3/D11 P1_4/D12 P1_5/D13/INT3 P1_6/D14/INT4 P1_7/D15/INT5 P2_0/AN2_0/A0(/D0/-) P2_1/AN2_1/A1(/D1/D0) P2_2/AN2_2/A2(/D2/D1) P2_3/AN2_3/A3(/D3/D2) P2_4/AN2_4/A4(/D4/D3) P2_5/AN2_5/A5(/D5/D4) P2_6/AN2_6/A6(/D6/D5) P2_7/AN2_7/A7(/D7/D6) VSS P3_0/A8(/-/D7) VCC2 P3_1/A9 P3_2/A10 P3_3/A11 P3_4/A12 P3_5/A13 P3_6/A14 P3_7/A15 P4_0/A16 P4_1/A17 M16C/6N Group (M16C/6N5) P4_2/A18 P4_3/A19 P4_4/CS0 P4_5/CS1 P4_6/CS2 P4_7/CS3 P5_0/WRL/WR P5_1/WRH/BHE P5_2/RD P5_3/BCLK P5_4/HLDA P5_5/HOLD P5_6/ALE P5_7/RDY/CLKOUT P6_0/CTS0/RTS0 P6_1/CLK0 P6_2/RXD0/SCL0 P6_3/TXD0/SDA0 P6_4/CTS1/RTS1/CTS0/CLKS1 P6_5/CLK1 P6_6/RXD1/SCL1 P6_7/TXD1/SDA1 P7_0/TXD2/SDA2/TA0OUT P7_1/RXD2/SCL2/TA0IN/TB5IN (1) P7_2/CLK2/TA1OUT/V NOTE: 1. P7_1 and P9_1 are N channel open-drain pins. Figure 1.4 Pin Assignments (Top View) (2) Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 6 of 84 P9_4/DA1/TB4IN P9_3/DA0/TB3IN P9_2/TB2IN/SOUT3 (1) P9_1/TB1IN/SIN3 P9_0/TB0IN/CLK3 BYTE CNVSS P8_7/XCIN P8_6/XCOUT RESET XOUT VSS XIN VCC1 P8_5/NMI P8_4/INT2/ZP P8_3/INT1 P8_2/INT0 P8_1/TA4IN/U P8_0/TA4OUT/U P7_7/TA3IN P7_6/TA3OUT P7_5/TA2IN/W P7_4/TA2OUT/W P7_3/CTS2/RTS2/TA1IN/V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Package: PLQP0100KB-A (100P6Q-A) Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) Table 1.3 List of Pin Names (1) Pin No. Control FP GP Pin 1 99 2 100 3 1 4 2 5 3 6 4 7 5 8 6 BYTE 9 7 CNVSS 10 8 XCIN 11 9 XCOUT ____________ 12 10 RESET 13 11 XOUT 14 12 VSS 15 13 XIN 16 14 VCC1 17 15 18 16 19 17 20 18 21 19 22 20 23 21 24 22 25 23 26 24 27 25 28 26 29 27 30 28 31 29 32 30 33 31 34 32 35 33 36 34 37 35 38 36 39 37 40 38 41 39 42 40 43 41 44 42 45 43 46 44 47 45 48 46 49 47 50 48 Port P9_6 P9_5 P9_4 P9_3 P9_2 P9_1 P9_0 Interrupt Pin Timer Pin UART Pin 1. Overview Analog CAN Module Bus Control Pin Pin Pin ANEX1 ANEX0 DA1 DA0 CTX0 CRX0 TB4IN TB3IN TB2IN TB1IN TB0IN SOUT3 SIN3 CLK3 P8_7 P8_6 _______ P8_5 P8_4 P8_3 P8_2 P8_1 P8_0 P7_7 P7_6 P7_5 P7_4 P7_3 P7_2 P7_1 P7_0 P6_7 P6_6 P6_5 P6_4 P6_3 P6_2 P6_1 P6_0 P5_7 P5_6 P5_5 P5_4 P5_3 P5_2 P5_1 P5_0 P4_7 P4_6 P4_5 P4_4 NMI ________ INT2 INT1 INT0 ZP ___ TA4IN/U TA4OUT/U TA3IN TA3OUT ____ TA2IN/W TA2OUT/W ___ TA1IN/V TA1OUT/V TA0IN/TB5IN TA0OUT __________ __________ CTS2/RTS2 CLK2 RXD2/SCL2 TXD2/SDA2 TXD1/SDA1 RXD1/SCL1 CLK1 _________ _________ _________ CTS1/RTS1/CTS0/CLKS1 TXD0/SDA0 RXD0/SCL0 CLK0 __________ __________ CTS0/RTS0 ________ RDY/CLKOUT ALE __________ HOLD __________ HLDA BCLK _____ RD _________ ________ WRH/BHE ________ ______ WRL/WR _______ CS3 _______ CS2 _______ CS1 _______ CS0 FP: PRQP0100JB-A (100P6S-A), GP: PLQP0100KB-A (100P6Q-A) Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 7 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) Table 1.4 List of Pin Names (2) Pin No. Control FP GP Pin 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 Port P4_3 P4_2 P4_1 P4_0 P3_7 P3_6 P3_5 P3_4 P3_3 P3_2 P3_1 VCC2 P3_0 VSS P2_7 P2_6 P2_5 P2_4 P2_3 P2_2 P2_1 P2_0 P1_7 P1_6 P1_5 P1_4 P1_3 P1_2 P1_1 P1_0 P0_7 P0_6 P0_5 P0_4 P0_3 P0_2 P0_1 P0_0 P10_7 P10_6 P10_5 P10_4 P10_3 P10_2 P10_1 AVSS P10_0 VREF AVCC P9_7 AN0 AN2_7 AN2_6 AN2_5 AN2_4 AN2_3 AN2_2 AN2_1 AN2_0 Interrupt Pin Timer Pin UART Pin 1. Overview Analog CAN Module Bus Control Pin Pin Pin A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8(/-/D7) A7(/D7/D6) A6(/D6/D5) A5(/D5/D4) A4(/D4/D3) A3(/D3/D2) A2(/D2/D1) A1(/D1/D0) A0(/D0/-) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ________ INT5 ________ INT4 ________ INT3 ______ KI3 ______ KI2 ______ KI1 ______ KI0 AN0_7 AN0_6 AN0_5 AN0_4 AN0_3 AN0_2 AN0_1 AN0_0 AN7 AN6 AN5 AN4 AN3 AN2 AN1 _____________ ADTRG FP: PRQP0100JB-A (100P6S-A), GP: PLQP0100KB-A (100P6Q-A) Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 8 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 1. Overview 1.6 Pin Functions Tables 1.5 to 1.7 list the Pin Functions. Table 1.5 Pin Functions (1) Signal Name Power supply input Analog power supply input Reset input CNVSS Pin Name VCC1, VCC2, VSS AVCC, AVSS _____________ I/O Type Description I Apply 4.2 to 5.5 V (T/V-ver.), 3.0 to 5.5 V (Normal-ver.) to the VCC1 and VCC2 pins and 0 V to the VSS pin. The VCC apply condition is that VCC2 = VCC1 (1). Applies the power supply for the A/D converter. Connect the AVCC pin to VCC1. Connect the AVSS pin to VSS. The MCU is in a reset state when applying "L" to the this pin. Switches processor mode. Connect this pin to VSS to when after a reset to start up in single-chip mode. Connect this pin to VCC1 to start up in microprocessor mode. Switches the data bus in external memory space. The data bus is 16-bit long when the this pin is held "L" and 8-bit long when the this pin is held "H". Set it to either one. Connect this pin to VSS when single-chip mode. Inputs and outputs data (D0 to D7) when these pins are set as the separate bus. Inputs and outputs data (D8 to D15) when external 16-bit data bus is set as the separate bus. Output address bits (A0 to A19). Input and output data (D0 to D7) and output address bits (A0 to A7) by time-sharing when external 8-bit data bus are set as the multiplexed bus. Input and output data (D0 to D7) and output address bits (A1 to A8) by time-sharing when external 16-bit data bus are set as the multiplexed bus. _______ _______ _______ _______ Output CS0 to CS3 signals. CS0 to CS3 are chip-select signals to specify an external space. ________ _________ ______ ________ _____ ________ _________ Output WRL, WRH, (WR, BHE), RD signals. WRL and WRH or ________ ______ BHE, and WR can be switched by program. ________ _________ _____ * WRL, WRH, and RD are selected ________ The WRL signal becomes "L" by writing data to an even address in an external memory space. _________ The WRH signal becomes "L" by writing data to an odd address in an_____ external memory space. The RD pin signal becomes "L" by reading data in an external memory space._____ ______ ________ * WR, ______ and RD are selected BHE, The WR signal becomes "L" by writing data in an external memory space. _____ The RD signal becomes "L" by reading data in an external memory space. ________ The BHE signal becomes "L" by accessing an odd address. ______ ________ _____ Select WR, BHE, and RD for an external 8-bit data bus. ALE is a signal to latch the address. __________ While the HOLD pin is held "L", the MCU is placed in a hold state. __________ In a hold state, HLDA outputs a "L" signal. ________ While applying a "L" signal to the RDY pin, the MCU is placed in a wait state. I I I RESET CNVSS External data bus width select input Bus control pins BYTE I D0 to D7 D8 to D15 A0 to A19 A0/D0 to A7/D7 I/O I/O O I/O A1/D0 to A8/D7 _______ _______ I/O CS0 to CS3 _________ ______ O O WRL/WR WRH/BHE ______ RD _________ ________ ALE __________ HOLD __________ O I O I HLDA ________ RDY I: Input O: Output I/O: Input/Output NOTE: 1. In this manual, hereafter, VCC refers to VCC1 unless otherwise noted. Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 9 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) Table 1.6 Pin Functions (2) Signal Name Main clock input Main clock output Sub clock input Sub clock output BCLK output Clock output INT interrupt input _______ NMI interrupt input Key input interrupt input Timer A XIN XOUT XCIN XCOUT BCLK CLKOUT ________ ________ INT0 to INT5 ________ NMI ______ ______ 1. Overview Pin Name I/O Type I O I O O O I I I I/O I I I O I O I/O I I O O O I/O I/O I I Description I/O pins for the main clock oscillation circuit. Connect a ceramic resonator or crystal oscillator between XIN and XOUT (1). To use the external clock, input the clock from XIN and leave XOUT open. I/O pins for a sub clock oscillation circuit. Connect a crystal oscillator between XCIN and XCOUT (1). To use the external clock, input the clock from XCIN and leave XCOUT open. Outputs the BCLK signal. The clock of the same cycle as fC, f8, or f32 is output. ______ Input pins for the_______ interrupt. INT Input pin for the NMI interrupt. Input pins for the key input interrupt. These are timer A0 to timer A4 I/O pins. These are timer A0 to timer A4 input pins. Input pin for the Z-phase. These are timer B0 to timer B5 input pins. These are Three-phase motor control output pins. These are transmit control input pins. These are receive control output pins. These are transfer clock I/O pins. These are serial data input pins. These are serial data input pins. These are serial data output pins. These are serial data output pins. This is output pin for transfer clock output from multiple pins function. These are serial data I/O pins. These are transfer clock I/O pins. (however, SCL2 for the N-channel open drain output.) Applies the reference voltage for the A/D converter and D/A converter. Analog input pins for the A/D converter. KI0 to KI3 TA0OUT to TA4OUT TA0IN to TA4IN ZP Timer B TB0IN to___ TB5IN ___ ____ Three-phase motor U, U, V, V, W, W control output __________ __________ Serial interface CTS0 to CTS2 __________ __________ RTS0 to RTS2 CLK0 to CLK3 RXD0 to RXD2 SIN3 TXD0 to TXD2 SOUT3 CLKS1 I2C mode SDA0 to SDA2 SCL0 to SCL2 VREF AN0 to AN7 AN0_0 to AN0_7 AN2_0 to AN2_7 _____________ ADTRG ANEX0 ANEX1 Reference voltage input A/D converter I I/O I O I This is an A/D trigger input pin. This is the extended analog input pin for the A/D converter, and is the output in external op-amp connection mode. This is the extended analog input pin for the A/D converter. These are the output pins for the D/A converter. This is the input pin for the CAN module. D/A converter CAN module I: Input DA0, DA1 CRX0 CTX0 O: Output This is the output pin for the CAN module. O I/O: Input/Output NOTE: 1. Ask the oscillator maker the oscillation characteristic. Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 10 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) Table 1.7 Pin Functions (3) Signal Name I/O port Pin Name P0_0 to P0_7 P1_0 to P1_7 P2_0 to P2_7 P3_0 to P3_7 P4_0 to P4_7 P5_0 to P5_7 P6_0 to P6_7 P7_0 to P7_7 P8_0 to P8_4 P8_6, P8_7 P9_0 to P9_7 P10_0 to P10_7 Input port I: Input P8_5 O: Output I _______ 1. Overview I/O Type Description 8-bit I/O ports in CMOS, having a direction register to select I/O an input or output. Each pin is set as an input port or output port. An input port can be set for a pull-up or for no pull-up in 4-bit unit by program. (however, P7_1 and P9_1 for the N-channel open drain output.) Input pin for the NMI interrupt. Pin states can be read by the P8_5 bit in the P8 register. I/O: Input/Output Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 11 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 2. Central Processing Unit (CPU) 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU Registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1, and FB configure a register bank. There are two register banks. b31 b15 b8 b7 b0 R2 R3 R0H (R0's high bits) R0L (R0's low bits) R1H (R1's high bits) R1L (R1's low bits) R2 R3 A0 A1 FB b19 b15 b0 Data Registers (1) Address Registers (1) Frame Base Registers (1) INTBH INTBL Interrupt Table Register The upper 4 bits of INTB are INTBH and the lower 16 bits of INTB are INTBL. b19 b0 PC b15 b0 Program Counter USP ISP SB b15 b0 User Stack Pointer Interrupt Stack Pointer Static Base Register FLG b15 b8 b7 b0 Flag Register IPL U I OBS Z DC Carry Flag Debug Flag Zero Flag Sign Flag Register Bank Select Flag Overflow Flag Interrupt Enable Flag Stack Pointer Select Flag Reserved Area Processor Interrupt Priority Level Reserved Area NOTE: 1. These registers comprise a register bank. There are two register banks. Figure 2.1 CPU Registers 2.1 Data Registers (R0, R1, R2, and R3) The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to R3 are the same as R0. The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers. R1H and R1L are the same as R0H and R0L. Conversely R2 and R0 can be combined for use as a 32-bit data register (R2R0). R3R1 is analogous to R2R0. 2.2 Address Registers (A0 and A1) The A0 register consists of 16 bits, and is used for address register indirect addressing and address register relative addressing. They also are used for transfers and arithmetic/logic operations. A1 is the same as A0. In some instructions, A1 and A0 can be combined for use as a 32-bit address register (A1A0). Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 12 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 2. Central Processing Unit (CPU) 2.3 Frame Base Register (FB) FB is configured with 16 bits, and is used for FB relative addressing. 2.4 Interrupt Table Register (INTB) INTB is configured with 20 bits, indicating the start address of an interrupt vector table. 2.5 Program Counter (PC) PC is configured with 20 bits, indicating the address of an instruction to be executed. 2.6 User Stack Pointer (USP), Interrupt Stack Pointer (ISP) Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG. 2.7 Static Base Register (SB) SB is configured with 16 bits, and is used for SB relative addressing. 2.8 Flag Register (FLG) FLG consists of 11 bits, indicating the CPU status. 2.8.1 Carry Flag (C Flag) This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. 2.8.2 Debug Flag (D Flag) This flag is used exclusively for debugging purpose. During normal use, set to 0. 2.8.3 Zero Flag (Z Flag) This flag is set to 1 when an arithmetic operation resulted in 0; otherwise, it is 0. 2.8.4 Sign Flag (S Flag) This flag is set to 1 when an arithmetic operation resulted in a negative value; otherwise, it is 0. 2.8.5 Register Bank Select Flag (B Flag) Register bank 0 is selected when this flag is 0; register bank 1 is selected when this flag is 1. 2.8.6 Overflow Flag (O Flag) This flag is set to 1 when the operation resulted in an overflow; otherwise, it is 0. 2.8.7 Interrupt Enable Flag (I Flag) This flag enables a maskable interrupt. Maskable interrupts are disabled when the I flag is 0, and are enabled when the I flag is 1. The I flag is set to 0 when the interrupt request is accepted. 2.8.8 Stack Pointer Select Flag (U Flag) ISP is selected when the U flag is 0; USP is selected when the U flag is 1. The U flag is set to 0 when a hardware interrupt request is accepted or an INT instruction for software interrupt Nos. 0 to 31 is executed. 2.8.9 Processor Interrupt Priority Level (IPL) IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than IPL, the interrupt request is enabled. 2.8.10 Reserved Area When white to this bit, write 0. When read, its content is undefined. Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 13 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 3. Memory 3. Memory Figure 3.1 shows a Memory Map. The address space extends the 1 Mbyte from address 00000h to FFFFFh. The internal ROM is allocated in a lower address direction beginning with address FFFFFh. For example, a 128-Kbyte internal ROM is allocated to the addresses from E0000h to FFFFFh. As for the flash memory version, 4-Kbyte space (block A) exists in 0F000h to 0FFFFh. 4-Kbyte space is mainly for storing data. In addition to storing data, 4-Kbyte space also can store programs. The fixed interrupt vector table is allocated to the addresses from FFFDCh to FFFFFh. Therefore, store the start address of each interrupt routine here. The internal RAM is allocated in an upper address direction beginning with address 00400h. For example, a 5-Kbyte internal RAM is allocated to the addresses from 00400h to 017FFh. In addition to storing data, the internal RAM also stores the stack used when calling subroutines and when interrupts are generated. The Special Function Registers (SFRs) are allocated to the addresses from 00000h to 003FFh. Peripheral function control registers are located here. Of the SFR, any area which has no functions allocated is reserved for future use and cannot be accessed by user. The special page vector table is allocated to the addresses from FFE00h to FFFDBh. This vector is used by the JMPS or JSRS instruction. For details, refer to M16C/60, M16C/20, M16C/Tiny Series Software Manual. In memory expansion and microprocessor modes, some areas are reserved for future use and cannot be used by users. 00000h SFR 00400h Internal RAM XXXXXh Reserved area (1) 0F000h 0FFFFh 10000h Internal ROM (data flash) (3) External area 27000h 28000h External area 80000h Internal RAM Capacity 5 Kbytes Address XXXXXh 017FFh Internal ROM (4) Capacity 128 Kbytes Address YYYYYh E0000h FFFFFh YYYYYh Reserved area (2) Internal ROM (program area) (4) FFFFFh Reserved area FFFDCh Undefined instruction FFE00h Special page vector table Overflow BRK instruction Address match Single step Oscillation stop and re-oscillation detection / watchdog timer DBC NMI Reset NOTES: 1. During memory expansion mode or microprocessor mode, cannot be used. 2. In memory expansion mode, cannot be used. 3. As for the flash memory version, 4-Kbyte space (block A) exists. 4. When using the masked ROM version, write nothing to internal ROM area. 5. Shown here is a memory map for the case where the PM10 bit in the PM1 register is 1 (block A enabled, addresses 10000h to 26FFFh for CS2 area). M16C/6N Group (M16C/6N5) has no device model expanded over 192 Kbytes of the internal ROM. Accordingly, set the PM13 bit to 0. Figure 3.1 Memory Map Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 14 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 4. Special Function Registers (SFRs) 4. Special Function Registers (SFRs) An SFR (Special Function Register) is a control register for a peripheral function. Tables 4.1 to 4.12 list the SFR Information. Table 4.1 SFR Information (1) (3) Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh Processor Mode Register 0 (1) Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1 Chip Select Control Register Address Match Interrupt Enable Register Protect Register Oscillation Stop Detection Register (2) Watchdog Timer Start Register Watchdog Timer Control Register Address Match Interrupt Register 0 Register Symbol After Reset PM0 PM1 CM0 CM1 CSR AIER PRCR CM2 WDTS WDC RMAD0 00000000b (CNVSS pin is "L") 00000011b (CNVSS pin is "H") 00001000b 01001000b 00100000b 00000001b XXXXXX00b XX000000b 0X000000b XXh 00XXXXXXb 00h 00h X0h 00h 00h X0h Address Match Interrupt Register 1 RMAD1 Chip Select Expansion Control Register PLL Control Register 0 Processor Mode Register 2 CSE PLC0 PM2 00h 0001X010b XXX00000b XXh XXh XXh XXh XXh XXh XXh XXh DMA0 Source Pointer SAR0 DMA0 Destination Pointer DAR0 DMA0 Transfer Counter TCR0 DMA0 Control Register DM0CON 00000X00b DMA1 Source Pointer SAR1 XXh XXh XXh XXh XXh XXh XXh XXh DMA1 Destination Pointer DAR1 DMA1 Transfer Counter TCR1 DMA1 Control Register DM1CON 00000X00b X: Undefined NOTES: 1. Bits PM00 and PM01 in the PM0 register do not change at software reset, watchdog timer reset and oscillation stop detection reset. 2. Bits CM20, CM21, and CM27 in the CM2 register do not change at oscillation stop detection reset. 3. Blank spaces are reserved. No access is allowed. Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 15 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) Table 4.2 SFR Information (2) (1) Address 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh Register CAN0 Wake-up Interrupt Control Register CAN0 Successful Reception Interrupt Control Register CAN0 Successful Transmission Interrupt Control Register INT3 Interrupt Control Register Timer B5 Interrupt Control Register Timer B4 Interrupt Control Register UART1 Bus Collision Detection Interrupt Control Register Timer B3 Interrupt Control Register UART0 Bus Collision Detection Interrupt Control Register INT5 Interrupt Control Register SI/O3 Interrupt Control Register INT4 Interrupt Control Register UART2 Bus Collision Detection Interrupt Control Register DMA0 Interrupt Control Register DMA1 Interrupt Control Register CAN0 Error Interrupt Control Register A/D Conversion Interrupt Control Register Key Input Interrupt Control Register UART2 Transmit Interrupt Control Register UART2 Receive Interrupt Control Register UART0 Transmit Interrupt Control Register UART0 Receive Interrupt Control Register UART1 Transmit Interrupt Control Register UART1 Receive Interrupt Control Register Timer A0 Interrupt Control Register Timer A1 Interrupt Control Register Timer A2 Interrupt Control Register Timer A3 Interrupt Control Register Timer A4 Interrupt Control Register Timer B0 Interrupt Control Register Timer B1 Interrupt Control Register Timer B2 Interrupt Control Register INT0 Interrupt Control Register INT1 Interrupt Control Register INT2 Interrupt Control Register 4. Special Function Registers (SFRs) Symbol C01WKIC C0RECIC C0TRMIC INT3IC TB5IC TB4IC U1BCNIC TB3IC U0BCNIC INT5IC S3IC INT4IC U2BCNIC DM0IC DM1IC C01ERRIC ADIC KUPIC S2TIC S2RIC S0TIC S0RIC S1TIC S1RIC TA0IC TA1IC TA2IC TA3IC TA4IC TB0IC TB1IC TB2IC INT0IC INT1IC INT2IC After Reset XXXXX000b XXXXX000b XXXXX000b XX00X000b XXXXX000b XXXXX000b XXXXX000b XX00X000b XX00X000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XX00X000b XX00X000b XX00X000b XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh CAN0 Message Box 0: Identifier / DLC CAN0 Message Box 0: Data Field CAN0 Message Box 0: Time Stamp CAN0 Message Box 1: Identifier / DLC CAN0 Message Box 1: Data Field CAN0 Message Box 1: Time Stamp X: Undefined NOTE: 1. Blank space is reserved. No access is allowed. Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 16 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) Table 4.3 SFR Information (3) Address 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h 00A1h 00A2h 00A3h 00A4h 00A5h 00A6h 00A7h 00A8h 00A9h 00AAh 00ABh 00ACh 00ADh 00AEh 00AFh 00B0h 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h 00B9h 00BAh 00BBh 00BCh 00BDh 00BEh 00BFh Register 4. Special Function Registers (SFRs) Symbol CAN0 Message Box 2: Identifier / DLC CAN0 Message Box 2: Data Field CAN0 Message Box 2: Time Stamp CAN0 Message Box 3: Identifier / DLC CAN0 Message Box 3: Data Field CAN0 Message Box 3: Time Stamp CAN0 Message Box 4: Identifier / DLC CAN0 Message Box 4: Data Field CAN0 Message Box 4: Time Stamp CAN0 Message Box 5: Identifier / DLC CAN0 Message Box 5: Data Field CAN0 Message Box 5: Time Stamp After Reset XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh X: Undefined Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 17 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) Table 4.4 SFR Information (4) Address 00C0h 00C1h 00C2h 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h 00CAh 00CBh 00CCh 00CDh 00CEh 00CFh 00D0h 00D1h 00D2h 00D3h 00D4h 00D5h 00D6h 00D7h 00D8h 00D9h 00DAh 00DBh 00DCh 00DDh 00DEh 00DFh 00E0h 00E1h 00E2h 00E3h 00E4h 00E5h 00E6h 00E7h 00E8h 00E9h 00EAh 00EBh 00ECh 00EDh 00EEh 00EFh 00F0h 00F1h 00F2h 00F3h 00F4h 00F5h 00F6h 00F7h 00F8h 00F9h 00FAh 00FBh 00FCh 00FDh 00FEh 00FFh Register 4. Special Function Registers (SFRs) Symbol CAN0 Message Box 6: Identifier / DLC CAN0 Message Box 6: Data Field CAN0 Message Box 6: Time Stamp CAN0 Message Box 7: Identifier / DLC CAN0 Message Box 7: Data Field CAN0 Message Box 7: Time Stamp CAN0 Message Box 8: Identifier / DLC CAN0 Message Box 8: Data Field CAN0 Message Box 8: Time Stamp CAN0 Message Box 9: Identifier / DLC CAN0 Message Box 9: Data Field CAN0 Message Box 9: Time Stamp After Reset XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh X: Undefined Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 18 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) Table 4.5 SFR Information (5) Address 0100h 0101h 0102h 0103h 0104h 0105h 0106h 0107h 0108h 0109h 010Ah 010Bh 010Ch 010Dh 010Eh 010Fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h 0119h 011Ah 011Bh 011Ch 011Dh 011Eh 011Fh 0120h 0121h 0122h 0123h 0124h 0125h 0126h 0127h 0128h 0129h 012Ah 012Bh 012Ch 012Dh 012Eh 012Fh 0130h 0131h 0132h 0133h 0134h 0135h 0136h 0137h 0138h 0139h 013Ah 013Bh 013Ch 013Dh 013Eh 013Fh Register 4. Special Function Registers (SFRs) Symbol CAN0 Message Box 10: Identifier / DLC CAN0 Message Box 10: Data Field CAN0 Message Box 10: Time Stamp CAN0 Message Box 11: Identifier / DLC CAN0 Message Box 11: Data Field CAN0 Message Box 11: Time Stamp CAN0 Message Box 12: Identifier / DLC CAN0 Message Box 12: Data Field CAN0 Message Box 12: Time Stamp CAN0 Message Box 13: Identifier / DLC CAN0 Message Box 13: Data Field CAN0 Message Box 13: Time Stamp After Reset XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh X: Undefined Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 19 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) Table 4.6 SFR Information (6) (1) Address 0140h 0141h 0142h 0143h 0144h 0145h 0146h 0147h 0148h 0149h 014Ah 014Bh 014Ch 014Dh 014Eh 014Fh 0150h 0151h 0152h 0153h 0154h 0155h 0156h 0157h 0158h 0159h 015Ah 015Bh 015Ch 015Dh 015Eh 015Fh 0160h 0161h 0162h 0163h 0164h 0165h 0166h 0167h 0168h 0169h 016Ah 016Bh 016Ch 016Dh 016Eh 016Fh 0170h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017Ah 017Bh 017Ch 017Dh 017Eh 017Fh Register 4. Special Function Registers (SFRs) Symbol CAN0 Message Box 14: Identifier /DLC CAN0 Message Box 14: Data Field CAN0 Message Box 14: Time Stamp CAN0 Message Box 15: Identifier /DLC CAN0 Message Box 15: Data Field CAN0 Message Box 15: Time Stamp CAN0 Global Mask Register C0GMR CAN0 Local Mask A Register C0LMAR CAN0 Local Mask B Register C0LMBR After Reset XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh X: Undefined NOTE: 1. Blank spaces are reserved. No access is allowed. Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 20 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) Table 4.7 SFR Information (7) (2) Address 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018Ah 018Bh 018Ch 018Dh 018Eh 018Fh 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019Ah 019Bh 019Ch 019Dh 019Eh 019Fh 01A0h 01A1h 01A2h 01A3h 01A4h 01A5h 01A6h 01A7h 01A8h 01A9h 01AAh 01ABh 01ACh 01ADh 01AEh 01AFh 01B0h 01B1h 01B2h 01B3h 01B4h 01B5h 01B6h 01B7h 01B8h 01B9h 01BAh 01BBh 01BCh 01BDh 01BEh 01BFh Register 4. Special Function Registers (SFRs) Symbol After Reset Flash Memory Control Register 1 (1) Flash Memory Control Register 0 (1) Address Match Interrupt Register 2 Address Match Interrupt Enable Register 2 Address Match Interrupt Register 3 FMR1 FMR0 RMAD2 AIER2 RMAD3 0X00XX0Xb 00000001b 00h 00h X0h XXXXXX00b 00h 00h X0h X: Undefined NOTES: 1. These registers are included in the flash memory version. Cannot be accessed by users in the mask ROM version. 2. Blank spaces are reserved. No access is allowed. Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 21 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) Table 4.8 SFR Information (8) (1) Address 01C0h 01C1h 01C2h 01C3h 01C4h 01C5h 01C6h 01C7h 01C8h 01C9h 01CAh 01CBh 01CCh 01CDh 01CEh 01CFh 01D0h 01D1h 01D2h 01D3h 01D4h 01D5h 01D6h 01D7h 01D8h 01D9h 01DAh 01DBh 01DCh 01DDh 01DEh 01DFh 01E0h 01E1h 01E2h 01E3h 01E4h 01E5h 01E6h 01E7h 01E8h 01E9h 01EAh 01EBh 01ECh 01EDh 01EEh 01EFh 01F0h 01F1h 01F2h 01F3h 01F4h 01F5h 01F6h 01F7h 01F8h 01F9h 01FAh 01FBh 01FCh 01FDh 01FEh 01FFh Register Timer B3, B4, B5 Count Start Flag Timer A1-1 Register Timer A2-1 Register Timer A4-1 Register Three-Phase PWM Control Register 0 Three-Phase PWM Control Register 1 Three-Phase Output Buffer Register 0 Three-Phase Output Buffer Register 1 Dead Time Timer Timer B2 Interrupt Generation Frequency Set Counter 4. Special Function Registers (SFRs) Symbol TBSR TA11 TA21 TA41 INVC0 INVC1 IDB0 IDB1 DTT ICTB2 After Reset 000XXXXXb XXh XXh XXh XXh XXh XXh 00h 00h 00111111b 00111111b XXh XXh Timer B3 Register Timer B4 Register Timer B5 Register TB3 TB4 TB5 XXh XXh XXh XXh XXh XXh Timer B3 Mode Register Timer B4 Mode Register Timer B5 Mode Register Interrupt Source Select Register 0 Interrupt Source Select Register 1 SI/O3 Transmit/Receive Register SI/O3 Control Register SI/O3 Bit Rate Register TB3MR TB4MR TB5MR IFSR0 IFSR1 S3TRR S3C S3BRG 00XX0000b 00XX0000b 00XX0000b 00XXX000b 00h XXh 01000000b XXh UART0 Special Mode Register 4 UART0 Special Mode Register 3 UART0 Special Mode Register 2 UART0 Special Mode Register UART1 Special Mode Register 4 UART1 Special Mode Register 3 UART1 Special Mode Register 2 UART1 Special Mode Register UART2 Special Mode Register 4 UART2 Special Mode Register 3 UART2 Special Mode Register 2 UART2 Special Mode Register UART2 Transmit/Receive Mode Register UART2 Bit Rate Register UART2 Transmit Buffer Register UART2 Transmit/Receive Control Register 0 UART2 Transmit/Receive Control Register 1 UART2 Receive Buffer Register U0SMR4 U0SMR3 U0SMR2 U0SMR U1SMR4 U1SMR3 U1SMR2 U1SMR U2SMR4 U2SMR3 U2SMR2 U2SMR U2MR U2BRG U2TB U2C0 U2C1 U2RB 00h 000X0X0Xb X0000000b X0000000b 00h 000X0X0Xb X0000000b X0000000b 00h 000X0X0Xb X0000000b X0000000b 00h XXh XXh XXh 00001000b 00000010b XXh XXh X: Undefined NOTE: 1. Blank spaces are reserved. No access is allowed. Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 22 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) Table 4.9 SFR Information (9) (1) Address 0200h 0201h 0202h 0203h 0204h 0205h 0206h 0207h 0208h 0209h 020Ah 020Bh 020Ch 020Dh 020Eh 020Fh 0210h 0211h 0212h 0213h 0214h 0215h 0216h 0217h 0218h 0219h 021Ah 021Bh 021Ch 021Dh 021Eh 021Fh 0220h 0221h 0222h 0223h 0224h 0225h 0226h 0227h 0228h 0229h 022Ah 022Bh 022Ch 022Dh 022Eh 022Fh 0230h 0231h 0232h 0233h 0234h 0235h 0236h 0237h 0238h 0239h 023Ah 023Bh 023Ch 023Dh 023Eh 023Fh Register CAN0 Message Control Register 0 CAN0 Message Control Register 1 CAN0 Message Control Register 2 CAN0 Message Control Register 3 CAN0 Message Control Register 4 CAN0 Message Control Register 5 CAN0 Message Control Register 6 CAN0 Message Control Register 7 CAN0 Message Control Register 8 CAN0 Message Control Register 9 CAN0 Message Control Register 10 CAN0 Message Control Register 11 CAN0 Message Control Register 12 CAN0 Message Control Register 13 CAN0 Message Control Register 14 CAN0 Message Control Register 15 CAN0 Control Register CAN0 Status Register CAN0 Slot Status Register CAN0 Interrupt Control Register CAN0 Extended ID Register CAN0 Configuration Register CAN0 Receive Error Count Register CAN0 Transmit Error Count Register CAN0 Time Stamp Register 4. Special Function Registers (SFRs) Symbol C0MCTL0 C0MCTL1 C0MCTL2 C0MCTL3 C0MCTL4 C0MCTL5 C0MCTL6 C0MCTL7 C0MCTL8 C0MCTL9 C0MCTL10 C0MCTL11 C0MCTL12 C0MCTL13 C0MCTL14 C0MCTL15 C0CTLR C0STR C0SSTR C0ICR C0IDR C0CONR C0RECR C0TECR C0TSR After Reset 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h X0000001b XX0X0000b 00h X0000001b 00h 00h 00h 00h 00h 00h XXh XXh 00h 00h 00h 00h CAN1 Control Register C1CTLR X0000001b XX0X0000b X: Undefined NOTE: 1. Blank spaces are reserved. No access is allowed. Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 23 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) Table 4.10 SFR Information (10) (1) Address 0240h 0241h 0242h 0243h 0244h 0245h 0246h 0247h 0248h 0249h 024Ah 024Bh 024Ch 024Dh 024Eh 024Fh 0250h 0251h 0252h 0253h 0254h 0255h 0256h 0257h 0258h 0259h 025Ah 025Bh 025Ch 025Dh 025Eh 025Fh 0260h 0261h 0262h 0263h 0264h 0265h 0266h 0267h 0268h 0269h 026Ah 026Bh 026Ch 026Dh 026Eh 026Fh 0270h to 0372h 0373h 0374h 0375h 0376h 0377h 0378h 0379h 037Ah 037Bh 037Ch 037Dh 037Eh 037Fh Register 4. Special Function Registers (SFRs) Symbol After Reset CAN0 Acceptance Filter Support Register C0AFS XXh XXh Peripheral Clock Select Register CAN0 Clock Select Register PCLKR CCLKR 00h 00h X: Undefined NOTE: 1. Blank spaces are reserved. No access is allowed. Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 24 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) Table 4.11 SFR Information (11) (2) Address 0380h 0381h 0382h 0383h 0384h 0385h 0386h 0387h 0388h 0389h 038Ah 038Bh 038Ch 038Dh 038Eh 038Fh 0390h 0391h 0392h 0393h 0394h 0395h 0396h 0397h 0398h 0399h 039Ah 039Bh 039Ch 039Dh 039Eh 039Fh 03A0h 03A1h 03A2h 03A3h 03A4h 03A5h 03A6h 03A7h 03A8h 03A9h 03AAh 03ABh 03ACh 03ADh 03AEh 03AFh 03B0h 03B1h 03B2h 03B3h 03B4h 03B5h 03B6h 03B7h 03B8h 03B9h 03BAh 03BBh 03BCh 03BDh 03BEh 03BFh Register Count Start Flag Clock Prescaler Reset Flag One-Shot Start Flag Trigger Select Register Up/Down Flag Timer A0 Register Timer A1 Register Timer A2 Register Timer A3 Register Timer A4 Register Timer B0 Register Timer B1 Register Timer B2 Register Timer A0 Mode Register Timer A1 Mode Register Timer A2 Mode Register Timer A3 Mode Register Timer A4 Mode Register Timer B0 Mode Register Timer B1 Mode Register Timer B2 Mode Register Timer B2 Special Mode Register UART0 Transmit/Receive Mode Register UART0 Bit Rate Register UART0 Transmit Buffer Register UART0 Transmit/Receive Control Register 0 UART0 Transmit/Receive Control Register 1 UART0 Receive Buffer Register UART1 Transmit/Receive Mode Register UART1 Bit Rate Register UART1 Transmit Buffer Register UART1 Transmit/Receive Control Register 0 UART1 Transmit/Receive Control Register 1 UART1 Receive Buffer Register UART Transmit/Receive Control Register 2 4. Special Function Registers (SFRs) Symbol TABSR CPSRF ONSF TRGSR UDF TA0 TA1 TA2 TA3 TA4 TB0 TB1 TB2 TA0MR TA1MR TA2MR TA3MR TA4MR TB0MR TB1MR TB2MR TB2SC U0MR U0BRG U0TB U0C0 U0C1 U0RB U1MR U1BRG U1TB U1C0 U1C1 U1RB UCON After Reset 00h 0XXXXXXXb 00h 00h 00h (1) XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh 00h 00h 00h 00h 00h 00XX0000b 00XX0000b 00XX0000b XXXXXX00b 00h XXh XXh XXh 00001000b 00XX0010b XXh XXh 00h XXh XXh XXh 00001000b 00XX0010b XXh XXh X0000000b DMA0 Request Source Select Register DMA1 Request Source Select Register CRC Data Register CRC Input Register DM0SL DM1SL CRCD CRCIN 00h 00h XXh XXh XXh X: Undefined NOTES: 1. Bits TA2P to TA4P in the UDF register are set to 0 after reset. However, the contents in these bits are undefined when read. 2. Blank spaces are reserved. No access is allowed. Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 25 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) Table 4.12 SFR Information (12) (2) Address 03C0h 03C1h 03C2h 03C3h 03C4h 03C5h 03C6h 03C7h 03C8h 03C9h 03CAh 03CBh 03CCh 03CDh 03CEh 03CFh 03D0h 03D1h 03D2h 03D3h 03D4h 03D5h 03D6h 03D7h 03D8h 03D9h 03DAh 03DBh 03DCh 03DDh 03DEh 03DFh 03E0h 03E1h 03E2h 03E3h 03E4h 03E5h 03E6h 03E7h 03E8h 03E9h 03EAh 03EBh 03ECh 03EDh 03EEh 03EFh 03F0h 03F1h 03F2h 03F3h 03F4h 03F5h 03F6h 03F7h 03F8h 03F9h 03FAh 03FBh 03FCh 03FDh 03FEh 03FFh Register A/D Register 0 A/D Register 1 A/D Register 2 A/D Register 3 A/D Register 4 A/D Register 5 A/D Register 6 A/D Register 7 4. Special Function Registers (SFRs) Symbol AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 After Reset XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh A/D Control Register 2 A/D Control Register 0 A/D Control Register 1 D/A Register 0 D/A Register 1 D/A Control Register ADCON2 ADCON0 ADCON1 DA0 DA1 DACON 00h 00000XXXb 00h 00h 00h 00h Port P0 Register Port P1 Register Port P0 Direction Register Port P1 Direction Register Port P2 Register Port P3 Register Port P2 Direction Register Port P3 Direction Register Port P4 Register Port P5 Register Port P4 Direction Register Port P5 Direction Register Port P6 Register Port P7 Register Port P6 Direction Register Port P7 Direction Register Port P8 Register Port P9 Register Port P8 Direction Register Port P9 Direction Register Port P10 Register Port P10 Direction Register P0 P1 PD0 PD1 P2 P3 PD2 PD3 P4 P5 PD4 PD5 P6 P7 PD6 PD7 P8 P9 PD8 PD9 P10 PD10 XXh XXh 00h 00h XXh XXh 00h 00h XXh XXh 00h 00h XXh XXh 00h 00h XXh XXh 00X00000b 00h XXh 00h Pull-up Control Register 0 Pull-up Control Register 1 Pull-up Control Register 2 Port Control Register PUR0 PUR1 PUR2 PCR 00h 00000000b (1) 00000010b 00h 00h X: Undefined NOTES: 1. At hardware reset, the register is as follows: 00000000b where "L" is input to the CNVSS pin 00000010b where "H" is input to the CNVSS pin At software reset, watchdog timer reset and oscillation stop detection reset, the register is as follows: 00000000b where bits PM01 to PM00 in the PM0 register are 00b (single-chip mode) 00000010b where bits PM01 to PM00 in the PM0 register are 01b (memory expansion mode) or 11b (microprocessor mode) 2. Blank spaces are reserved. No access is allowed. Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 26 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 5. Electric Characteristics (T/V-ver.) 5. Electrical Characteristics 5.1 Electrical Characteristics (T/V-ver.) Table 5.1 Absolute Maximum Ratings Symbol VCC AVCC VI Analog supply voltage _____________ Parameter Supply voltage (VCC1 = VCC2) Input voltage RESET, CNVSS, BYTE, P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7, VREF, XIN P7_1, P9_1 Condition VCC = AVCC VCC = AVCC Rated Value -0.3 to 6.5 -0.3 to 6.5 -0.3 to VCC+0.3 Unit V V V -0.3 to 6.5 -0.3 to VCC+0.3 V V VO Output voltage P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7, XOUT Pd Topr P7_1, P9_1 Power dissipation Operating ambient During MCU operation temperature During flash memory program and erase operation -0.3 to 6.5 Topr = 25C 700 T version: -40 to 85 V version: -40 to 125 (option) 0 to 60 -65 to 150 V mW C Tstg Storage temperature C option: All options are on request basis. Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 27 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) Table 5.2 Recommended Operating Conditions (1) Symbol VCC AVCC VSS AVSS VIH Parameter Supply voltage (VCC1 = VCC2) Analog supply voltage Supply voltage Analog supply voltage HIGH input voltage (1) 5. Electric Characteristics (T/V-ver.) Min. 4.2 Standard Max. Typ. 5.0 VCC 0 0 VCC 5.5 Unit V V V V V P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, 0.8 VCC P7_0, P7_2 to P7_7, P8_0 to P8_7, P9_0, P9_2 to P9_7, _____________ P10_0 to P10_7, XIN, RESET, CNVSS, BYTE P7_1, P9_1 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 (During single-chip mode) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 (Data input during memory expansion and microprocessor modes) 0.5 VCC 0 0.8 VCC 0.8 VCC 6.5 VCC VCC 0.2 VCC V V V V VIL LOW input voltage P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, _____________ XIN, RESET, CNVSS, BYTE P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 (During single-chip mode) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 (Data input during memory expansion and microprocessor modes) 0 0 0.2 VCC 0.16 VCC -10.0 V V mA IOH(peak) HIGH peak P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, output current P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7 HIGH average P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, output current P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, output current P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 LOW peak LOW average P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, output current P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 IOH(avg) -5.0 mA IOL(peak) 10.0 mA IOL(avg) 5.0 mA NOTES: 1. Referenced to VCC = 4.2 to 5.5 V at Topr = -40 to 85C unless otherwise specified. 2. Average output current values during 100 ms period. 3. The total IOL(peak) for ports P0, P1, P2, P8_6, P8_7, P9, and P10 must be 80 mA max. The total IOL(peak) for ports P3, P4, P5, P6, P7, and P8_0 to P8_4 must be 80 mA max. The total IOH(peak) for ports P0, P1, and P2 must be -40 mA max. The total IOH(peak) for ports P3, P4, and P5 must be -40 mA max. The total IOH(peak) for ports P6, P7, and P8_0 to P8_4 must be -40 mA max. The total IOH(peak) for ports P8_6, P8_7, P9, and P10 must be -40 mA max. Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 28 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) Table 5.3 Recommended Operating Conditions (2) Symbol f(XIN) f(XCIN) f(Ring) f(PLL) f(BCLK) tsu(PLL) NOTES: f(XIN) operating maximum frequency [MHz] (1) 5. Electric Characteristics (T/V-ver.) Parameter Main clock input oscillation No wait Mask ROM version VCC = 4.2 to 5.5 V frequency (2) (3) (4) Min. 0 Standard Max. Typ. 16 32.768 1 50 20 20 20 Unit MHz kHz MHz MHz MHz ms Flash memory version Sub clock oscillation frequency On-chip oscillation frequency PLL clock oscillation frequency CPU operation clock PLL frequency synthesizer stabilization wait time VCC = 4.2 to 5.5 V 16 0 1. Referenced to VCC = 4.2 to 5.5 V at Topr = -40 to 85C unless otherwise specified. 2. Relationship between main clock oscillation frequency and supply voltage is shown right. 3. Execute program/erase of flash memory by VCC = 5.0 0.5 V. 4. When using over 16 MHz, use PLL clock. PLL clock oscillation frequency which can be used is 16 MHz or 20 MHz. Main clock input oscillation frequency (Mask ROM version / Flash memory version: no wait) 16.0 0.0 4.2 5.5 VCC [V] (main clock: no division) Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 29 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) Table 5.4 Electrical Characteristics (1) Symbol VOH HIGH output voltage Parameter (1) 5. Electric Characteristics (T/V-ver.) Measuring Condition V P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, IOH = -5 mA P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7 VCC V P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, IOH = -200 A VOH HIGH output VCC-0.3 voltage P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7 IOH = -1 mA VCC V 3.0 XOUT HIGHPOWER VOH HIGH output voltage IOH = -0.5 mA VCC 3.0 LOWPOWER 2.5 V With no load applied XCOUT HIGHPOWER HIGH output voltage 1.6 With no load applied LOWPOWER 2.0 V P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, IOL = 5 mA VOL LOW output voltage P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 V P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, IOL = 200 A 0.45 VOL LOW output voltage P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 V VOL IOL = 1 mA XOUT HIGHPOWER LOW output 2.0 voltage IOL = 0.5 mA LOWPOWER 2.0 0 V With no load applied XCOUT HIGHPOWER LOW output voltage 0 With no load applied LOWPOWER _________ _______ V 0.2 VT+-VT- Hysteresis 1.0 HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN, ________ ________ _______ _____________ _________ _________ INT0 to INT5, NMI, ADTRG, CTS0 to CTS2, SCL0 to SCL2, SDA0 to SDA2, CLK0 to CLK3, _____ _____ TA0OUT to TA4OUT, KI0 to KI3, RXD0 to RXD2, SIN3 _____________ V 2.5 VT+-VT- Hysteresis RESET 0.2 HIGH input A 5.0 IIH P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, VI = 5 V current P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, ____________ XIN, RESET, CNVSS, BYTE LOW input -5.0 A P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, VI = 0 V IIL current P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 ____________ P10_0 to P10_7, to P9_7, XIN, RESET, CNVSS, BYTE k 170 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, VI = 0 V 50 RPULLUP Pull-up 30 resistance P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7 Feedback resistance M XIN 1.5 RfXIN M Feedback resistance XCIN 15 RfXCIN V RAM retention voltage 2.0 At stop mode VRAM NOTES: 1. Referenced to VCC = 4.2 to 5.5 V, VSS = 0 V at Topr = -40 to 85C, f(BCLK) = 20 MHz unless otherwise specified. Standard Min. Typ. Max. VCC VCC-2.0 Unit Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 30 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) Table 5.5 Electrical Characteristics (2) Symbol ICC Power supply current Parameter (1) 5. Electric Characteristics (T/V-ver.) Measuring Condition f(BCLK) = 20 MHz, PLL operation, No division On-chip oscillation, No division Flash memory f(BCLK) = 20 MHz, PLL operation, No division On-chip oscillation, No division Flash memory f(BCLK) = 10 MHz, program erase Mask ROM VCC = 5 V Flash memory f(BCLK) = 10 MHz, VCC = 5 V f(BCLK) = 32 kHz, Low power dissipation mode, ROM (2) Min. In single-chip mode, Mask ROM Standard Typ. Max. 16 28 Unit mA the output pins are (VCC = 4.2 to 5.5 V) open and other pins are VSS. 1 18 30 mA mA 1.8 15 25 25 mA mA mA A Flash memory f(BCLK) = 32 kHz, Low power dissipation mode, RAM (2) 25 A f(BCLK) = 32 kHz, Low power dissipation mode, Flash memory (2) 420 A Mask ROM On-chip oscillation, Flash memory Wait mode f(BCLK) = 32 kHz, Wait mode (3) 50 8.5 A A , 3.0 A Oscillation capacity High f(BCLK) = 32 kHz, Wait mode (3) , 0.8 3.0 A Oscillation capacity Low Stop mode, Topr = 25C NOTES: 1. Referenced to VCC = 4.2 to 5.5 V, VSS = 0 V at Topr = -40 to 85C, f(BCLK) = 20 MHz unless otherwise specified. 2. This indicates the memory in which the program to be executed exists. 3. With one timer operated using fC32. Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 31 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) Table 5.6 A/D Conversion Characteristics Symbol - INL Parameter Resolution Integral nonlinearity error 8 bits - Absolute accuracy 8 bits DNL - - RLADDER tCONV Differential nonlinearity error Offset error Gain error Resistor ladder 10-bit conversion time, sample & hold available 8-bit conversion time, sample & hold available tSAMP VREF VIA NOTES: Sampling time Reference voltage Analog input voltage VREF = VCC = 5 V, AD = 10 MHz VREF = VCC VREF = VCC = 5 V, AD = 10 MHz 10 bits 10 bits (1) 5. Electric Characteristics (T/V-ver.) Measuring Condition VREF = VCC VREF ANEX0, ANEX1 input, AN0 to AN7 input, = VCC AN0_0 to AN0_7 input, AN2_0 to AN2_7 input = 5 V External operation amp connection mode VREF = AVCC = VCC = 5 V VREF ANEX0, ANEX1 input, AN0 to AN7 input, = VCC AN0_0 to AN0_7 input, AN2_0 to AN2_7 input = 5 V External operation amp connection mode VREF = AVCC = VCC = 5 V Min. Standard Typ. Max. 10 3 7 2 3 7 2 1 3 3 Unit Bit LSB LSB LSB LSB LSB LSB LSB LSB LSB k s s s 10 3.3 2.8 0.3 2.0 0 40 VCC VREF V V 1. Referenced to VCC = AVCC = VREF = 4.2 to 5.5 V, VSS = AVSS = 0 V, -40 to 85C unless otherwise specified. 2. AD frequency must be 10 MHz or less. 3. When sample & hold is disabled, AD frequency must be 250kHz or more in addition to a limit of NOTE 2. When sample & hold is enabled, AD frequency must be 1MHz or more in addition to a limit of NOTE 2. Table 5.7 D/A conversion Characteristics Symbol - - tsu RO IVREF Resolution Absolute accuracy Setup time Output resistance Parameter (1) Measuring condition Min. Standard Typ. Max. 8 1.0 3 Unit Bits % s k mA 4 (NOTE 2) 10 20 1.5 Reference power supply input current NOTES: 1. Referenced to VCC = AVCC = VREF = 4.2 to 5.5 V, VSS = AVSS = 0 V, -40 to 85C unless otherwise specified. 2. This applies when using one D/A converter, with the DAi register (i = 0, 1) for the unused D/A converter set to 00h. The resistor ladder of the A/D converter is not included. Also, the IVREF will flow even if VREF is disconnected by the ADCON1 register. Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 32 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) Table 5.8 Power Supply Circuit Timing Characteristics Symbol td(P-R) td(R-S) td(W-S) Parameter 5. Electric Characteristics (T/V-ver.) Measuring Condition Min. Time for internal power supply stabilization during powering-on VCC = 4.2 to 5.5 V STOP release time Low power dissipation mode wait mode release time Standard Typ. Max. 2 150 150 Unit ms s s td(P-R) Time for internal power supply stabilization during powering-on VCC td(P-R) CPU clock td(R-S) STOP release time td(W-S) Low power dissipation mode wait mode release time Interrupt for (a) Stop mode release or (b) Wait mode release CPU clock (a) (b) td(R-S) td(W-S) Figure 5.1 Power Supply Circuit Timing Diagram Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 33 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 5. Electric Characteristics (T/V-ver.) Timing Requirements VCC (Referenced to VCC = 5 V, VSS = 0 V, at Topr = -40 to 85C unless otherwise specified) Table 5.9 External Clock Input (XIN Input) Symbol tC tw(H) tw(L) tr tf External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock rise time External clock fall time Parameter Standard Min. Max. 62.5 25 25 15 15 =5V Unit ns ns ns ns ns Table 5.10 Memory Expansion Mode and Microprocessor Mode Symbol tac1(RD-DB) tac2(RD-DB) tac3(RD-DB) tsu(DB-RD) tsu(RDY-BCLK) Parameter Data input access time (for setting with no wait) Data input access time (for setting with wait) Data input access time (when accessing multiplexed bus area) Data input setup time ________ Standard Unit Min. Max. (NOTE 1) ns (NOTE 2) ns (NOTE 3) 40 30 40 0 0 0 ns ns ns ns ns ns ns RDY input setup time __________ tsu(HOLD-BCLK) HOLD input setup time th(RD-DB) Data input hold time ________ th(BCLK-RDY) RDY input hold time __________ th(BCLK-HOLD) HOLD input hold time NOTES: 1. Calculated according to the BCLK frequency as follows: 0.5 10 - 45 [ns] f(BCLK) 9 2. Calculated according to the BCLK frequency as follows: (n -0.5) 10 f(BCLK) 9 - 45 [ns] n is "2" for 1-wait setting, "3" for 2-wait setting and "4" for 3-wait setting. 3. Calculated according to the BCLK frequency as follows: (n -0.5) 109 - 45 [ns] f(BCLK) n is "2" for 2-wait setting, "3" for 3-wait setting. Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 34 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 5. Electric Characteristics (T/V-ver.) Timing Requirements VCC (Referenced to VCC = 5 V, VSS = 0 V, at Topr = -40 to 85C unless otherwise specified) Table 5.11 Timer A Input (Counter Input in Event Counter Mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. Max. 100 40 40 =5V Unit ns ns ns Table 5.12 Timer A Input (Gating Input in Timer Mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. Max. 400 200 200 Unit ns ns ns Table 5.13 Timer A Input (External Trigger Input in One-shot Timer Mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. Max. 200 100 100 Unit ns ns ns Table 5.14 Timer A Input (External Trigger Input in Pulse Width Modulation Mode) Symbol tw(TAH) tw(TAL) TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. Max. 100 100 Unit ns ns Table 5.15 Timer A Input (Counter Increment/decrement Input in Event Counter Mode) Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) TAiOUT input cycle time TAiOUT input HIGH pulse width TAiOUT input LOW pulse width TAiOUT input setup time TAiOUT input hold time Parameter Standard Min. Max. 2000 1000 1000 400 400 Unit ns ns ns ns ns Table 5.16 Timer A Input (Two-phase Pulse Input in Event Counter Mode) Symbol TAiIN input cycle time tsu(TAIN-TAOUT) TAiOUT input setup time tsu(TAOUT-TAIN) TAiIN input setup time tc(TA) Parameter Standard Max. Min. 800 200 200 Unit ns ns ns Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 35 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 5. Electric Characteristics (T/V-ver.) Timing Requirements VCC (Referenced to VCC = 5 V, VSS = 0 V, at Topr = -40 to 85C unless otherwise specified) Table 5.17 Timer B Input (Counter Input in Event Counter Mode) Symbol Parameter TBiIN input cycle time (counted on one edge) TBiIN input HIGH pulse width (counted on one edge) TBiIN input LOW pulse width (counted on one edge) TBiIN input cycle time (counted on both edges) TBiIN input HIGH pulse width (counted on both edges) TBiIN input LOW pulse width (counted on both edges) Standard Min. Max. 100 40 40 200 80 80 =5V Unit ns ns ns ns ns ns tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Table 5.18 Timer B Input (Pulse Period Measurement Mode) Symbol Parameter TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width Standard Min. Max. 400 200 200 Unit ns ns ns tc(TB) tw(TBH) tw(TBL) Table 5.19 Timer B Input (Pulse Width Measurement Mode) Symbol Parameter TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width Standard Min. Max. 400 200 200 Unit ns ns ns tc(TB) tw(TBH) tw(TBL) Table 5.20 A/D Trigger Input Symbol Parameter _____________ tC(AD) tw(ADL) ADTRG input cycle time (trigger able minimum) _____________ Standard Min. Max. 1000 125 Unit ns ns ADTRG input LOW pulse width Table 5.21 Serial Interface Symbol Parameter CLKi input cycle time CLKi input HIGH pulse width CLKi input LOW pulse width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time _______ tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) Standard Min. Max. 200 100 100 80 0 70 90 Unit ns ns ns ns ns ns ns Table 5.22 External Interrupt INTi Input Symbol Parameter _______ tw(INH) tw(INL) INTi input HIGH pulse width _______ INTi input LOW pulse width Standard Min. Max. 250 250 Unit ns ns Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 36 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 5. Electric Characteristics (T/V-ver.) Switching Characteristics VCC (Referenced to VCC = 5 V, VSS = 0 V, at Topr = -40 to 85 C unless otherwise specified) Table 5.23 Memory Expansion Mode and Microprocessor Mode (for setting with no wait) Symbol Parameter Address output delay time Address output hold time (in relation to BCLK) Address output hold time (in relation to RD) Address output hold time (in relation to WR) Chip select output delay time Chip select output hold time (in relation to BCLK) ALE signal output delay time ALE signal output hold time RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (in relation to BCLK) Data output hold time (in relation to BCLK) Data output delay time (in relation to WR) Data output hold time (in relation to WR) __________ =5V Measuring Condition Figure 5.2 td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) td(BCLK-HLDA) Standard Min. Max. 25 4 0 (NOTE 1) 25 4 15 -4 25 0 25 0 40 4 (NOTE 2) (NOTE 1) 40 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (3) (3) HLDA output delay time NOTES: 1. Calculated according to the BCLK frequency as follows: 0.5 10 - 10 [ns] f(BCLK) 9 2. Calculated according to the BCLK frequency as follows: 0.5 10 - 40 [ns] f(BCLK) 9 f(BCLK) is 12.5 MHz or less. 3. This standard value shows the timing when the output is off, and does not show hold time of data bus. Hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = - CR ln (1 - VOL / VCC) by a circuit of the right figure. For example, when VOL = 0.2 VCC, C = 30 pF, R =1 k, hold time of output "L" level is t = - 30 pF 1 k ln (1 - 0.2 VCC / VCC) = 6.7 ns. R DBi C P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 30 pF Figure 5.2 Port P0 to P10 Measurement Circuit Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 37 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 5. Electric Characteristics (T/V-ver.) Switching Characteristics VCC (Referenced to VCC = 5 V, VSS = 0 V, at Topr = -40 to 85 C unless otherwise specified) =5V Table 5.24 Memory Expansion Mode and Microprocessor Mode (for 1- to 3-wait setting and external area access) Symbol Parameter Address output delay time Address output hold time (in relation to BCLK) Address output hold time (in relation to RD) Address output hold time (in relation to WR) Chip select output delay time Chip select output hold time (in relation to BCLK) ALE signal output delay time ALE signal output hold time RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (in relation to BCLK) Data output hold time (in relation to BCLK) Data output delay time (in relation to WR) Data output hold time (in relation to WR) __________ Measuring Condition Figure 5.2 td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) td(BCLK-HLDA) Standard Min. Max. 25 4 0 (NOTE 1) 25 4 15 -4 25 0 25 0 40 4 (NOTE 2) (NOTE 1) 40 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (3) (3) HLDA output delay time NOTES: 1. Calculated according to the BCLK frequency as follows: 0.5 10 - 10 [ns] f(BCLK) 9 2. Calculated according to the BCLK frequency as follows: (n - 0.5) 10 - 40 [ns] f(BCLK) 9 n is "1" for 1-wait setting, "2" for 2-wait setting and "3" for 3-wait setting. When n = 1, f(BCLK) is 12.5 MHz or less. 3. This standard value shows the timing when the output is off, and does not show hold time of data bus. Hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = - CR ln (1 - VOL / VCC) by a circuit of the right figure. For example, when VOL = 0.2 VCC, C = 30 pF, R =1 k, hold time of output "L" level is t = - 30 pF 1 k ln (1 - 0.2 VCC / VCC) = 6.7 ns. R DBi C Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 38 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 5. Electric Characteristics (T/V-ver.) Switching Characteristics VCC (Referenced to VCC = 5 V, VSS = 0 V, at Topr = -40 to 85 C unless otherwise specified) Table 5.25 Memory Expansion Mode and Microprocessor Mode (for 2- to 3-wait setting, external area access and multiplexed bus selection) Symbol Parameter Address output delay time Address output hold time (in relation to BCLK) Address output hold time (in relation to RD) Address output hold time (in relation to WR) Chip select output delay time Chip select output hold time (in relation to BCLK) Chip select output hold time (in relation to RD) Chip select output hold time (in relation to WR) RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (in relation to BCLK) Data output hold time (in relation to BCLK) Data output delay time (in relation to WR) Data output hold time (in relation to WR) __________ =5V Measuring Condition Figure 5.2 td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) th(RD-CS) th(WR-CS) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) td(BCLK-HLDA) Standard Min. Max. 25 4 (NOTE 1) (NOTE 1) 25 4 (NOTE 1) (NOTE 1) 25 0 25 0 40 4 (NOTE 2) (NOTE 1) 40 15 -4 (NOTE 3) (NOTE 4) 0 0 8 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns HLDA output delay time ALE signal output delay time (in relation to BCLK) ALE signal output hold time (in relation to BCLK) ALE signal output delay time (in relation to Address) ALE signal output hold time (in relation to Address) RD signal output delay from the end of Address WR signal output delay from the end of Address Address output floating start time td(BCLK-ALE) th(BCLK-ALE) td(AD-ALE) th(ALE-AD) td(AD-RD) td(AD-WR) tdZ(RD-AD) NOTES: 1. Calculated according to the BCLK frequency as follows: 0.5 109 - 10 [ns] f(BCLK) 2. Calculated according to the BCLK frequency as follows: (n -0.5) 10 f(BCLK) 9 - 40 [ns] n is "2" for 2-wait setting, "3" for 3-wait setting. 3. Calculated according to the BCLK frequency as follows: 0.5 10 - 25 [ns] f(BCLK) 9 4. Calculated according to the BCLK frequency as follows: 0.5 109 - 15 [ns] f(BCLK) Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 39 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 5. Electric Characteristics (T/V-ver.) VCC = 5 V XIN input tr tw(H) tr tc tc(TA) tw(TAH) TAiIN input tw(TAL) tc(UP) tw(UPH) TAiOUT input tw(UPL) TAiOUT input (Up/down input) tw(L) During event counter mode TAiIN input (When count on falling edge is selected) th(TIN--UP) tsu(UP--TIN) TAiIN input (When count on rising edge is selected) Two-phase pulse input in event counter mode tC(TA) TAiIN input tsu(TAIN--TAOUT) TAiOUT input tsu(TAOUT--TAIN) tc(TB) tw(TBH) TBiIN input tw(TBL) tc(AD) tw(ADL) ADTRG input tc(CK) tw(CKH) CLKi tw(CKL) TXDi td(C--Q) RXDi tw(INL) INTi input tw(INH) tsu(D--C) th(C--D) th(C--Q) tsu(TAIN--TAOUT) tsu(TAOUT--TAIN) Figure 5.3 Timing Diagram (1) Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 40 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 5. Electric Characteristics (T/V-ver.) Memory Expansion Mode and Microprocessor Mode (Effective for setting with wait) VCC = 5 V BCLK RD (Separate bus) WR, WRL, WRH (Separate bus) RD (Multiplexed bus) WR, WRL, WRH (Multiplexed bus) RDY input tsu(RDY-BCLK) th(BCLK-RDY) (Common to setting with wait and setting without wait) BCLK tsu(HOLD-BCLK) HOLD input th(BCLK-HOLD) HLDA output P0, P1, P2, P3, P4, P5_0 to P5_2 (1) td(BCLK-HLDA) td(BCLK-HLDA) Hi-Z NOTE: 1. The above pins are set to high-impedance regardless of the input level of the BYTE pin, the PM06 bit in the PM0 register, and the PM11 bit in the PM1 register. Measuring conditions : VCC = 5 V Input timing voltage : Determined with VIL = 1.0 V, VIH = 4.0 V Output timing voltage: Determined with VOL = 2.5 V, VOH = 2.5 V Figure 5.4 Timing Diagram (2) Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 41 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 5. Electric Characteristics (T/V-ver.) Memory Expansion Mode and Microprocessor Mode (For setting with no wait) Read timing BCLK td(BCLK-CS) 25ns.max VCC = 5 V th(BCLK-CS) 4ns.min CSi tcyc td(BCLK-AD) 25ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min th(RD-AD) 0ns.min ALE td(BCLK-RD) 25ns.max th(BCLK-RD) 0ns.min RD tac1(RD-DB) (0.5 tcyc-45)ns.max Hi-Z DBi tSU(DB-RD) 40ns.min th(RD-DB) 0ns.min Write timing BCLK td(BCLK-CS) 25ns.max th(BCLK-CS) 4ns.min CSi tcyc td(BCLK-AD) 25ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min th(WR-AD) (0.5 tcyc-10)ns.min ALE td(BCLK-WR) 25ns.max th(BCLK-WR) 0ns.min WR,WRL, WRH td(BCLK-DB) 40ns.max Hi-Z th(BCLK-DB) 4ns.min DBi td(DB-WR) 1 tcyc = f(BCLK) th(WR-DB) (0.5 tcyc-40)ns.min (0.5 tcyc-10)ns.min Measuring conditions : VCC = 5 V Input timing voltage : VIL = 0.8 V, VIH = 2.0 V Output timing voltage : VOL = 0.4 V, VOH = 2.4 V Figure 5.5 Timing Diagram (3) Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 42 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 5. Electric Characteristics (T/V-ver.) Memory Expansion Mode and Microprocessor Mode (For 1-wait setting and external area access) Read timing BCLK td(BCLK-CS) 25ns.max VCC = 5 V th(BCLK-CS) 4ns.min CSi tcyc td(BCLK-AD) 25ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min th(RD-AD) 0ns.min ALE td(BCLK-RD) 25ns.max th(BCLK-RD) 0ns.min RD tac2(RD-DB) (1.5 tcyc-45)ns.max DBi Hi-Z th(RD-DB) tSU(DB-RD) 40ns.min 0ns.min Write timing BCLK td(BCLK-CS) 25ns.max th(BCLK-CS) 4ns.min CSi tcyc td(BCLK-AD) 25ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min th(WR-AD) (0.5 tcyc-10)ns.min ALE td(BCLK-WR) 25ns.max th(BCLK-WR) 0ns.min WR,WRL, WRH td(BCLK-DB) 40ns.max Hi-Z th(BCLK-DB) 4ns.min DBi td(DB-WR) 1 tcyc = f(BCLK) (0.5 tcyc-40)ns.min th(WR-DB) (0.5 tcyc-10)ns.min Measuring conditions : VCC = 5 V Input timing voltage : VIL = 0.8 V, VIH = 2.0 V Output timing voltage : VOL = 0.4 V, VOH = 2.4 V Figure 5.6 Timing Diagram (4) Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 43 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 5. Electric Characteristics (T/V-ver.) Memory Expansion Mode and Microprocessor Mode (For 2-wait setting and external area access) Read timing tcyc VCC = 5 V BCLK td(BCLK-CS) 25ns.max th(BCLK-CS) 4ns.min CSi td(BCLK-AD) 25ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min th(RD-AD) 0ns.min ALE td(BCLK-RD) 25ns.max th(BCLK-RD) 0ns.min RD tac2(RD-DB) (2.5 tcyc-45)ns.max DBi Hi-Z tSU(DB-RD) 40ns.min th(RD-DB) 0ns.min Write timing tcyc BCLK td(BCLK-CS) 25ns.max th(BCLK-CS) 4ns.min CSi td(BCLK-AD) 25ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 25ns.max th(WR-AD) th(BCLK-ALE) -4ns.min (0.5 tcyc-10)ns.min ALE td(BCLK-WR) 25ns.max th(BCLK-WR) 0ns.min WR, WRL WRH td(BCLK-DB) 40ns.max th(BCLK-DB) 4ns.min DBi Hi-Z td(DB-WR) (1.5 tcyc-40)ns.min th(WR-DB) (0.5 tcyc-10)ns.min tcyc = 1 f(BCLK) Measuring conditions : VCC = 5 V Input timing voltage : VIL = 0.8 V, VIH = 2.0 V Output timing voltage : VOL = 0.4 V, VOH = 2.4 V Figure 5.7 Timing Diagram (5) Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 44 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 5. Electric Characteristics (T/V-ver.) Memory Expansion Mode and Microprocessor Mode (For 3-wait setting and external area access) Read timing tcyc VCC = 5 V BCLK td(BCLK-CS) 25ns.max th(BCLK-CS) 4ns.min CSi td(BCLK-AD) 25ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min th(RD-AD) 0ns.min ALE td(BCLK-RD) 25ns.max th(BCLK-RD) 0ns.min RD tac2(RD-DB) (3.5 tcyc-45)ns.max DBi Hi-Z tSU(DB-RD) 40ns.min th(RD-DB) 0ns.min Write timing tcyc BCLK td(BCLK-CS) 25ns.max th(BCLK-CS) 4ns.min CSi td(BCLK-AD) 25ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min th(WR-AD) (0.5 tcyc-10)ns.min ALE td(BCLK-WR) 25ns.max th(BCLK-WR) 0ns.min WR, WRL WRH td(BCLK-DB) 40ns.max th(BCLK-DB) 4ns.min DBi Hi-Z td(DB-WR) (2.5 tcyc-40)ns.min th(WR-DB) (0.5 tcyc-10)ns.min 1 tcyc = f(BCLK) Measuring conditions : VCC = 5 V Input timing voltage : VIL = 0.8 V, VIH = 2.0 V Output timing voltage : VOL = 0.4 V, VOH = 2.4 V Figure 5.8 Timing Diagram (6) Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 45 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 5. Electric Characteristics (T/V-ver.) Memory Expansion Mode and Microprocessor Mode (For 1- or 2-wait setting, external area access and multiplexed bus selection) Read timing BCLK td(BCLK-CS) 25ns.max tcyc (0.5 tcyc-10)ns.min VCC = 5 V th(RD-CS) th(BCLK-CS) 4ns.min CSi td(AD-ALE) (0.5 tcyc-25)ns.min (0.5 tcyc-15)ns.min th(ALE-AD) ADi /DBi Address tdZ(RD-AD) 8ns.max Data input tac3(RD-DB) tSU(DB-RD) 40ns.min Address th(RD-DB) 0ns.min (1.5 tcyc-45)ns.max td(AD-RD) td(BCLK-AD) 25ns.max 0ns.min th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min th(RD-AD) (0.5 tcyc-10)ns.min ALE td(BCLK-RD) 25ns.max th(BCLK-RD) 0ns.min RD Write timing BCLK td(BCLK-CS) 25ns.max tcyc (0.5 tcyc-10)ns.min th(WR-CS) th(BCLK-CS) 4ns.min CSi td(BCLK-DB) 40ns.max th(BCLK-DB) 4ns.min ADi /DBi td(AD-ALE) Address Data output td(DB-WR) (1.5 tcyc-40)ns.min Address th(WR-DB) (0.5 tcyc-10)ns.min (0.5 tcyc-25)ns.min td(BCLK-AD) 25ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min td(AD-WR) 0ns.min th(WR-AD) (0.5 tcyc-10)ns.min ALE td(BCLK-WR) 25ns.max th(BCLK-WR) 0ns.min WR,WRL, WRH 1 f(BCLK) tcyc = Measuring conditions : VCC = 5 V Input timing voltage : VIL = 0.8 V, VIH = 2.0 V Output timing voltage : VOL = 0.4 V, VOH = 2.4 V Figure 5.9 Timing Diagram (7) Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 46 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 5. Electric Characteristics (T/V-ver.) Memory Expansion Mode and Microprocessor Mode (For 3-wait setting, external area access and multiplexed bus selection) Read timing tcyc VCC = 5 V BCLK td(BCLK-CS) 25ns.max (0.5 tcyc-10)ns.min th(RD-CS) th(BCLK-CS) 4ns.min CSi td(AD-ALE) (0.5 tcyc-25)ns.min ADi /DBi ADi BHE (no multiplex) 25ns.max (0.5 tcyc-15)ns.min th(ALE-AD) Address td(BCLK-AD) tdZ(RD-AD) td(AD-RD) 0ns.min 8ns.max Data input th(RD-DB) tac3(RD-DB) (2.5 tcyc-45)ns.max tSU(DB-RD) 40ns.min 0ns.min th(BCLK-AD) 4ns.min td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min th(RD-AD) (0.5 tcyc-10)ns.min ALE td(BCLK-RD) 25ns.max th(BCLK-RD) 0ns.min RD Write timing tcyc BCLK td(BCLK-CS) 25ns.max (0.5 tcyc-10)ns.min th(WR-CS) th(BCLK-CS) 4ns.min CSi td(BCLK-DB) 40ns.max th(BCLK-DB) 4ns.min ADi /DBi td(AD-ALE) Address Data output td(DB-WR) (2.5 tcyc-40)ns.min (0.5 tcyc-25)ns.min th(WR-DB) (0.5 tcyc-10)ns.min td(BCLK-AD) 25ns.max th(BCLK-AD) 4ns.min ADi BHE (no multiplex) td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min th(WR-AD) td(AD-WR) (0.5 tcyc-10)ns.min 0ns.min ALE td(BCLK-WR) WR, WRL WRH tcyc = 1 f(BCLK) 25ns.max th(BCLK-WR) 0ns.min Measuring conditions : VCC = 5 V Input timing voltage : VIL = 0.8 V, VIH = 2.0 V Output timing voltage : VOL = 0.4 V, VOH = 2.4 V Figure 5.10 Timing Diagram (8) Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 47 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 5. Electric Characteristics (Normal-ver.) 5.2 Electrical Characteristics (Normal-ver.) Table 5.26 Absolute Maximum Ratings Symbol VCC AVCC VI Analog supply voltage _____________ Parameter Supply voltage (VCC1 = VCC2) Input voltage RESET, CNVSS, BYTE, P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7, VREF, XIN P7_1, P9_1 Condition VCC = AVCC VCC = AVCC Rated Value -0.3 to 6.5 -0.3 to 6.5 -0.3 to VCC+0.3 Unit V V V -0.3 to 6.5 -0.3 to VCC+0.3 V V VO Output voltage P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7, XOUT Pd Topr P7_1, P9_1 Power dissipation Operating ambient During MCU operation temperature During flash memory program and erase operation -0.3 to 6.5 Topr = 25C 700 -40 to 85 0 to 60 -65 to 150 V mW C Tstg Storage temperature C Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 48 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) Table 5.27 Recommended Operating Conditions (1) Symbol VCC AVCC VSS AVSS VIH Parameter Supply voltage (VCC1 = VCC2) Analog supply voltage Supply voltage Analog supply voltage HIGH input voltage (1) 5. Electric Characteristics (Normal-ver.) Min. 3.0 Standard Max. Typ. 5.0 VCC 0 0 VCC 5.5 Unit V V V V V P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, 0.8 VCC P7_0, P7_2 to P7_7, P8_0 to P8_7, P9_0, P9_2 to P9_7, _____________ P10_0 to P10_7, XIN, RESET, CNVSS, BYTE P7_1, P9_1 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 (During single-chip mode) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 (Data input during memory expansion and microprocessor modes) 0.5 VCC 0 0.8 VCC 0.8 VCC 6.5 VCC VCC 0.2 VCC V V V V VIL LOW input voltage P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, _____________ XIN, RESET, CNVSS, BYTE P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 (During single-chip mode) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 (Data input during memory expansion and microprocessor modes) 0 0 0.2 VCC 0.16 VCC -10.0 V V mA IOH(peak) HIGH peak P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, output current P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7 HIGH average P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, output current P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, output current P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 LOW peak LOW average P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, output current P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 IOH(avg) -5.0 mA IOL(peak) 10.0 mA IOL(avg) 5.0 mA NOTES: 1. Referenced to VCC = 3.0 to 5.5 V at Topr = -40 to 85C unless otherwise specified. 2. Average output current values during 100 ms period. 3. The total IOL(peak) for ports P0, P1, P2, P8_6, P8_7, P9, and P10 must be 80 mA max. The total IOL(peak) for ports P3, P4, P5, P6, P7, and P8_0 to P8_4 must be 80 mA max. The total IOH(peak) for ports P0, P1, and P2 must be -40 mA max. The total IOH(peak) for ports P3, P4, and P5 must be -40 mA max. The total IOH(peak) for ports P6, P7, and P8_0 to P8_4 must be -40 mA max. The total IOH(peak) for ports P8_6, P8_7, P9, and P10 must be -40 mA max. Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 49 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) Table 5.28 Recommended Operating Conditions (2) Symbol f(XIN) f(XCIN) f(Ring) f(PLL) f(BCLK) tsu(PLL) NOTES: Parameter (1) 5. Electric Characteristics (Normal-ver.) Min. 0 Standard Max. Typ. 16 32.768 1 50 24 24 20 Unit MHz kHz MHz MHz MHz ms Main clock input oscillation No wait Mask ROM version VCC = 3.0 to 5.5 V frequency (2) (3) (4) Flash memory version Sub clock oscillation frequency On-chip oscillation frequency PLL clock oscillation frequency CPU operation clock PLL frequency synthesizer stabilization wait time f(XIN) operating maximum frequency [MHz] 16 VCC = 3.0 to 5.5 V 0 1. Referenced to VCC = 3.0 to 5.5 V at Topr = -40 to 85C unless otherwise specified. 2. Relationship between main clock oscillation frequency and supply voltage is shown right. 3. Execute program/erase of flash memory by VCC = 3.3 0.3 V or VCC = 5.0 0.5 V. 4. When using over 16 MHz, use PLL clock. PLL clock oscillation frequency which can be used is 16 MHz, 20 MHz or 24 MHz. Main clock input oscillation frequency (Mask ROM version / Flash memory version: no wait) 16.0 0.0 3.0 5.5 VCC [V] (main clock: no division) Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 50 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) Table 5.29 A/D Conversion Characteristics Symbol - INL Parameter Resolution Integral nonlinearity error 10 bits (1) 5. Electric Characteristics (Normal-ver.) Measuring Condition VREF = VCC VREF ANEX0, ANEX1 input, AN0 to AN7 input, = VCC AN0_0 to AN0_7 input, AN2_0 to AN2_7 input = 5 V External operation amp connection mode VREF ANEX0, ANEX1 input, AN0 to AN7 input, = VCC AN0_0 to AN0_7 input, AN2_0 to AN2_7 input = 3.3 V External operation amp connection mode Min. Standard Typ. Max. 10 3 7 5 7 2 3 7 5 7 2 1 3 3 Unit Bit LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB k s s s 8 bits - Absolute accuracy 10 bits VREF = AVCC = VCC = 5.0 V, 3.3 V VREF ANEX0, ANEX1 input, AN0 to AN7 input, = VCC AN0_0 to AN0_7 input, AN2_0 to AN2_7 input = 5 V External operation amp connection mode VREF ANEX0, ANEX1 input, AN0 to AN7 input, = VCC AN0_0 to AN0_7 input, AN2_0 to AN2_7 input = 3.3 V External operation amp connection mode 8 bits DNL - - RLADDER tCONV Differential nonlinearity error Offset error Gain error Resistor ladder 10-bit conversion time, sample & hold available 8-bit conversion time, sample & hold available tSAMP VREF VIA NOTES: Sampling time Reference voltage Analog input voltage VREF = AVCC = VCC = 5.0 V, 3.3 V VREF = VCC VREF = VCC = 5 V, AD = 10 MHz VREF = VCC = 5 V, AD = 10 MHz 10 3.3 2.8 0.3 2.0 0 40 VCC VREF V V 1. Referenced to VCC = AVCC = VREF = 3.3 to 5.5 V, VSS = AVSS = 0 V, -40 to 85C unless otherwise specified. 2. AD frequency must be 10 MHz or less. 3. When sample & hold is disabled, AD frequency must be 250 kHz or more in addition to a limit of NOTE 2. When sample & hold is enabled, AD frequency must be 1 MHz or more in addition to a limit of NOTE 2. Table 5.30 D/A conversion Characteristics Symbol - - tsu RO IVREF NOTES: Resolution Absolute accuracy Setup time Output resistance Reference power supply input current Parameter (1) Measuring Condition Min. Standard Typ. Max. 8 1.0 3 Unit Bits % s k mA 4 (NOTE 2) 10 20 1.5 1. Referenced to VCC = AVCC = VREF = 3.3 to 5.5 V, VSS = AVSS = 0 V, -40 to 85C unless otherwise specified. 2. This applies when using one D/A converter, with the DAi register (i = 0, 1) for the unused D/A converter set to 00h. The resistor ladder of the A/D converter is not included. Also, the current IVREF always flows even though VREF may have been set to be unconnected by the ADCON1 register. Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 51 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) Table 5.31 Power Supply Circuit Timing Characteristics Symbol td(P-R) td(R-S) td(W-S) Parameter 5. Electric Characteristics (Normal-ver.) Measuring Condition Min. Time for internal power supply stabilization during powering-on VCC = 3.0 to 5.5 V STOP release time Low power dissipation mode wait mode release time Standard Typ. Max. 2 150 150 Unit ms s s td(P-R) Time for internal power supply stabilization during powering-on VCC td(P-R) CPU clock td(R-S) STOP release time td(W-S) Low power dissipation mode wait mode release time Interrupt for (a) Stop mode release or (b) Wait mode release CPU clock (a) (b) td(R-S) td(W-S) Figure 5.11 Power Supply Circuit Timing Diagram Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 52 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) Table 5.32 Electrical Characteristics (1) Symbol VOH HIGH output voltage (1) 5. Electric Characteristics (Normal-ver.) VCC = 5V Unit V VOH HIGH output voltage VOH HIGH output voltage HIGH output voltage VOL LOW output voltage VOL LOW output voltage VOL LOW output voltage LOW output voltage VT+-VT- Hysteresis Standard Parameter Measuring Condition Min. Typ. Max. VCC P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, IOH = -5 mA VCC-2.0 P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7 VCC P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, IOH = -200 A VCC-0.3 P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7 IOH = -1 mA VCC 3.0 XOUT HIGHPOWER IOH = -0.5 mA VCC 3.0 LOWPOWER 2.5 With no load applied XCOUT HIGHPOWER 1.6 With no load applied LOWPOWER 2.0 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, IOL = 5 mA P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, IOL = 200 A 0.45 P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 IOL = 1 mA XOUT HIGHPOWER 2.0 IOL = 0.5 mA LOWPOWER 2.0 0 With no load applied XCOUT HIGHPOWER 0 With no load applied LOWPOWER _________ _______ 0.2 1.0 HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN, ________ ________ _______ _____________ _________ _________ V V V V V V V V INT0 to INT5, NMI, ADTRG, CTS0 to CTS2, SCL0 to SCL2, SDA0 to SDA2, CLK0 to CLK3, _____ _____ TA0OUT to TA4OUT, KI0 to KI3, RXD0 to RXD2, SIN3 _____________ VT+-VT- Hysteresis RESET HIGH input IIH P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, current P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 ____________ P10_0 to P10_7, to P9_7, XIN, RESET, CNVSS, BYTE LOW input P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, IIL current P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 ____________ P10_0 to P10_7, to P9_7, XIN, RESET, CNVSS, BYTE P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, RPULLUP Pull-up resistance P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7 Feedback resistance XIN RfXIN Feedback resistance XCIN RfXCIN RAM retention voltage VRAM NOTES: 0.2 VI = 5 V 2.5 5.0 V A VI = 0 V -5.0 A VI = 0 V 30 50 170 k 1.5 15 At stop mode 2.0 M M V 1. Referenced to VCC = 4.2 to 5.5 V, VSS = 0 V at Topr = -40 to 85C, f(BCLK) = 24 MHz unless otherwise specified. Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 53 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) Table 5.33 Electrical Characteristics (2) Symbol ICC Power supply current Parameter (1) 5. Electric Characteristics (Normal-ver.) Measuring Condition f(BCLK) = 24 MHz, PLL operation, No division On-chip oscillation, No division Flash memory f(BCLK) = 24 MHz, PLL operation, No division On-chip oscillation, No division Flash memory f(BCLK) = 10 MHz, program erase Mask ROM VCC = 5 V Flash memory f(BCLK) = 10 MHz, VCC = 5 V f(BCLK) = 32 kHz, Low power dissipation mode, ROM (2) Min. In single-chip mode, Mask ROM Standard Typ. Max. 16 32 Unit mA the output pins are (VCC = 3.0 to 5.5 V) open and other pins are VSS. 1 20 34 mA mA 1.8 15 25 25 mA mA mA A Flash memory f(BCLK) = 32 kHz, Low power dissipation mode, RAM (2) 25 A f(BCLK) = 32 kHz, Low power dissipation mode, Flash memory (2) 420 A Mask ROM On-chip oscillation, Flash memory Wait mode f(BCLK) = 32 kHz, Wait mode (3) 50 8.5 A A , 3.0 A Oscillation capacity High f(BCLK) = 32 kHz, Wait mode (3) , 0.8 3.0 A Oscillation capacity Low Stop mode, Topr = 25C NOTES: 1. Referenced to VCC = 3.0 to 5.5 V, VSS = 0 V at Topr = -40 to 85C, f(BCLK) = 24 MHz unless otherwise specified. 2. This indicates the memory in which the program to be executed exists. 3. With one timer operated using fC32. Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 54 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 5. Electric Characteristics (Normal-ver.) Timing Requirements VCC (Referenced to VCC = 5 V, VSS = 0 V, at Topr = -40 to 85C unless otherwise specified) Table 5.34 External Clock Input (XIN Input) Symbol tC tw(H) tw(L) tr tf External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock rise time External clock fall time Parameter Standard Min. Max. 62.5 25 25 15 15 =5V Unit ns ns ns ns ns Table 5.35 Memory Expansion Mode and Microprocessor Mode Symbol tac1(RD-DB) tac2(RD-DB) tac3(RD-DB) tsu(DB-RD) tsu(RDY-BCLK) Parameter Data input access time (for setting with no wait) Data input access time (for setting with wait) Data input access time (when accessing multiplexed bus area) Data input setup time ________ Standard Unit Min. Max. (NOTE 1) ns (NOTE 2) ns (NOTE 3) 40 30 40 0 0 0 ns ns ns ns ns ns ns RDY input setup time __________ tsu(HOLD-BCLK) HOLD input setup time th(RD-DB) Data input hold time ________ th(BCLK-RDY) RDY input hold time __________ th(BCLK-HOLD) HOLD input hold time NOTES: 1. Calculated according to the BCLK frequency as follows: 0.5 10 - 45 [ns] f(BCLK) 9 2. Calculated according to the BCLK frequency as follows: (n -0.5) 10 f(BCLK) 9 - 45 [ns] n is "2" for 1-wait setting, "3" for 2-wait setting and "4" for 3-wait setting. 3. Calculated according to the BCLK frequency as follows: (n -0.5) 109 - 45 [ns] f(BCLK) n is "2" for 2-wait setting, "3" for 3-wait setting. Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 55 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 5. Electric Characteristics (Normal-ver.) Timing Requirements VCC (Referenced to VCC = 5 V, VSS = 0 V, at Topr = -40 to 85C unless otherwise specified) Table 5.36 Timer A Input (Counter Input in Event Counter Mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. Max. 100 40 40 =5V Unit ns ns ns Table 5.37 Timer A Input (Gating Input in Timer Mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. Max. 400 200 200 Unit ns ns ns Table 5.38 Timer A Input (External Trigger Input in One-shot Timer Mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. Max. 200 100 100 Unit ns ns ns Table 5.39 Timer A Input (External Trigger Input in Pulse Width Modulation Mode) Symbol tw(TAH) tw(TAL) TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. Max. 100 100 Unit ns ns Table 5.40 Timer A Input (Counter Increment/decrement Input in Event Counter Mode) Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) TAiOUT input cycle time TAiOUT input HIGH pulse width TAiOUT input LOW pulse width TAiOUT input setup time TAiOUT input hold time Parameter Standard Min. Max. 2000 1000 1000 400 400 Unit ns ns ns ns ns Table 5.41 Timer A Input (Two-phase Pulse Input in Event Counter Mode) Symbol TAiIN input cycle rime tsu(TAIN-TAOUT) TAiOUT input setup time tsu(TAOUT-TAIN) TAiIN input setup time tc(TA) Parameter Standard Max. Min. 800 200 200 Unit ns ns ns Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 56 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 5. Electric Characteristics (Normal-ver.) Timing Requirements VCC (Referenced to VCC = 5 V, VSS = 0 V, at Topr = -40 to 85C unless otherwise specified) Table 5.42 Timer B Input (Counter Input in Event Counter Mode) Symbol Parameter TBiIN input cycle time (counted on one edge) TBiIN input HIGH pulse width (counted on one edge) TBiIN input LOW pulse width (counted on one edge) TBiIN input cycle time (counted on both edges) TBiIN input HIGH pulse width (counted on both edges) TBiIN input LOW pulse width (counted on both edges) Standard Min. Max. 100 40 40 200 80 80 =5V Unit ns ns ns ns ns ns tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Table 5.43 Timer B Input (Pulse Period Measurement Mode) Symbol Parameter TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width Standard Min. Max. 400 200 200 Unit ns ns ns tc(TB) tw(TBH) tw(TBL) Table 5.44 Timer B Input (Pulse Width Measurement Mode) Symbol Parameter TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width Standard Min. Max. 400 200 200 Unit ns ns ns tc(TB) tw(TBH) tw(TBL) Table 5.45 A/D Trigger Input Symbol Parameter _____________ tC(AD) tw(ADL) ADTRG input cycle time (trigger able minimum) _____________ Standard Min. Max. 1000 125 Unit ns ns ADTRG input LOW pulse width Table 5.46 Serial Interface Symbol Parameter CLKi input cycle time CLKi input HIGH pulse width CLKi input LOW pulse width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time _______ tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) Standard Min. Max. 200 100 100 80 0 70 90 Unit ns ns ns ns ns ns ns Table 5.47 External Interrupt INTi Input Symbol Parameter _______ tw(INH) tw(INL) INTi input HIGH pulse width _______ INTi input LOW pulse width Standard Min. Max. 250 250 Unit ns ns Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 57 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 5. Electric Characteristics (Normal-ver.) Switching Characteristics VCC (Referenced to VCC = 5 V, VSS = 0 V, at Topr = -40 to 85 C unless otherwise specified) Table 5.48 Memory Expansion Mode and Microprocessor Mode (for setting with no wait) Symbol Parameter Address output delay time Address output hold time (in relation to BCLK) Address output hold time (in relation to RD) Address output hold time (in relation to WR) Chip select output delay time Chip select output hold time (in relation to BCLK) ALE signal output delay time ALE signal output hold time RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (in relation to BCLK) Data output hold time (in relation to BCLK) Data output delay time (in relation to WR) Data output hold time (in relation to WR) __________ =5V Measuring Condition Figure 5.12 td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) td(BCLK-HLDA) Standard Min. Max. 25 4 0 (NOTE 1) 25 4 15 -4 25 0 25 0 40 4 (NOTE 2) (NOTE 1) 40 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (3) (3) HLDA output delay time NOTES: 1. Calculated according to the BCLK frequency as follows: 0.5 10 - 10 [ns] f(BCLK) 9 2. Calculated according to the BCLK frequency as follows: 0.5 10 - 40 [ns] f(BCLK) 9 f(BCLK) is 12.5 MHz or less. 3. This standard value shows the timing when the output is off, and does not show hold time of data bus. Hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = - CR ln (1 - VOL / VCC) by a circuit of the right figure. For example, when VOL = 0.2 VCC, C = 30 pF, R =1 k, hold time of output "L" level is t = - 30 pF 1 k ln (1 - 0.2 VCC / VCC) = 6.7 ns. R DBi C P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 30 pF Figure 5.12 Port P0 to P10 Measurement Circuit Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 58 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 5. Electric Characteristics (Normal-ver.) Switching Characteristics VCC (Referenced to VCC = 5 V, VSS = 0 V, at Topr = -40 to 85 C unless otherwise specified) =5V Table 5.49 Memory Expansion Mode and Microprocessor Mode (for 1- to 3-wait setting and external area access) Symbol Parameter Address output delay time Address output hold time (in relation to BCLK) Address output hold time (in relation to RD) Address output hold time (in relation to WR) Chip select output delay time Chip select output hold time (in relation to BCLK) ALE signal output delay time ALE signal output hold time RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (in relation to BCLK) Data output hold time (in relation to BCLK) Data output delay time (in relation to WR) Data output hold time (in relation to WR) __________ Measuring Condition Figure 5.12 td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) td(BCLK-HLDA) Standard Min. Max. 25 4 0 (NOTE 1) 25 4 15 -4 25 0 25 0 40 4 (NOTE 2) (NOTE 1) 40 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (3) (3) HLDA output delay time NOTES: 1. Calculated according to the BCLK frequency as follows: 0.5 10 - 10 [ns] f(BCLK) 9 2. Calculated according to the BCLK frequency as follows: (n - 0.5) 10 - 40 [ns] f(BCLK) 9 n is "1" for 1-wait setting, "2" for 2-wait setting and "3" for 3-wait setting. When n = 1, f(BCLK) is 12.5 MHz or less. 3. This standard value shows the timing when the output is off, and does not show hold time of data bus. Hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = - CR ln (1 - VOL / VCC) by a circuit of the right figure. For example, when VOL = 0.2 VCC, C = 30 pF, R =1 k, hold time of output "L" level is t = - 30 pF 1 k ln (1 - 0.2 VCC / VCC) = 6.7 ns. R DBi C Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 59 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 5. Electric Characteristics (Normal-ver.) Switching Characteristics VCC (Referenced to VCC = 5 V, VSS = 0 V, at Topr = -40 to 85 C unless otherwise specified) Table 5.50 Memory Expansion Mode and Microprocessor Mode (for 2- to 3-wait setting, external area access and multiplexed bus selection) Symbol Parameter Address output delay time Address output hold time (in relation to BCLK) Address output hold time (in relation to RD) Address output hold time (in relation to WR) Chip select output delay time Chip select output hold time (in relation to BCLK) Chip select output hold time (in relation to RD) Chip select output hold time (in relation to WR) RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (in relation to BCLK) Data output hold time (in relation to BCLK) Data output delay time (in relation to WR) Data output hold time (in relation to WR) __________ =5V Measuring Condition Figure 5.12 td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) th(RD-CS) th(WR-CS) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) td(BCLK-HLDA) Standard Min. Max. 25 4 (NOTE 1) (NOTE 1) 25 4 (NOTE 1) (NOTE 1) 25 0 25 0 40 4 (NOTE 2) (NOTE 1) 40 15 -4 (NOTE 3) (NOTE 4) 0 0 8 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns HLDA output delay time ALE signal output delay time (in relation to BCLK) ALE signal output hold time (in relation to BCLK) ALE signal output delay time (in relation to Address) ALE signal output hold time (in relation to Address) RD signal output delay from the end of Address WR signal output delay from the end of Address Address output floating start time td(BCLK-ALE) th(BCLK-ALE) td(AD-ALE) th(ALE-AD) td(AD-RD) td(AD-WR) tdZ(RD-AD) NOTES: 1. Calculated according to the BCLK frequency as follows: 0.5 109 - 10 [ns] f(BCLK) 2. Calculated according to the BCLK frequency as follows: (n -0.5) 10 f(BCLK) 9 - 40 [ns] n is "2" for 2-wait setting, "3" for 3-wait setting. 3. Calculated according to the BCLK frequency as follows: 0.5 10 - 25 [ns] f(BCLK) 9 4. Calculated according to the BCLK frequency as follows: 0.5 109 - 15 [ns] f(BCLK) Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 60 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 5. Electric Characteristics (Normal-ver.) VCC = 5 V XIN input tr tw(H) tr tc tc(TA) tw(TAH) TAiIN input tw(TAL) tc(UP) tw(UPH) TAiOUT input tw(UPL) TAiOUT input (Up/down input) tw(L) During event counter mode TAiIN input (When count on falling edge is selected) th(TIN--UP) tsu(UP--TIN) TAiIN input (When count on rising edge is selected) Two-phase pulse input in event counter mode tC(TA) TAiIN input tsu(TAIN--TAOUT) TAiOUT input tsu(TAOUT--TAIN) tc(TB) tw(TBH) TBiIN input tw(TBL) tc(AD) tw(ADL) ADTRG input tc(CK) tw(CKH) CLKi tw(CKL) TXDi td(C--Q) RXDi tw(INL) INTi input tw(INH) tsu(D--C) th(C--D) th(C--Q) tsu(TAIN--TAOUT) tsu(TAOUT--TAIN) Figure 5.13 Timing Diagram (1) Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 61 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 5. Electric Characteristics (Normal-ver.) Memory Expansion Mode and Microprocessor Mode (Effective for setting with wait) VCC = 5 V BCLK RD (Separate bus) WR, WRL, WRH (Separate bus) RD (Multiplexed bus) WR, WRL, WRH (Multiplexed bus) RDY input tsu(RDY-BCLK) th(BCLK-RDY) (Common to setting with wait and setting without wait) BCLK tsu(HOLD-BCLK) HOLD input th(BCLK-HOLD) HLDA output P0, P1, P2, P3, P4, P5_0 to P5_2 (1) td(BCLK-HLDA) td(BCLK-HLDA) Hi-Z NOTE: 1. The above pins are set to high-impedance regardless of the input level of the BYTE pin, the PM06 bit in the PM0 register, and the PM11 bit in the PM1 register. Measuring conditions : VCC = 5 V Input timing voltage : Determined with VIL = 1.0 V, VIH = 4.0 V Output timing voltage: Determined with VOL = 2.5 V, VOH = 2.5 V Figure 5.14 Timing Diagram (2) Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 62 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 5. Electric Characteristics (Normal-ver.) Memory Expansion Mode and Microprocessor Mode (For setting with no wait) Read timing BCLK td(BCLK-CS) 25ns.max VCC = 5 V th(BCLK-CS) 4ns.min CSi tcyc td(BCLK-AD) 25ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min th(RD-AD) 0ns.min ALE td(BCLK-RD) 25ns.max th(BCLK-RD) 0ns.min RD tac1(RD-DB) (0.5 tcyc-45)ns.max Hi-Z DBi tSU(DB-RD) 40ns.min th(RD-DB) 0ns.min Write timing BCLK td(BCLK-CS) 25ns.max th(BCLK-CS) 4ns.min CSi tcyc td(BCLK-AD) 25ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min th(WR-AD) (0.5 tcyc-10)ns.min ALE td(BCLK-WR) 25ns.max th(BCLK-WR) 0ns.min WR,WRL, WRH td(BCLK-DB) 40ns.max Hi-Z th(BCLK-DB) 4ns.min DBi td(DB-WR) 1 tcyc = f(BCLK) th(WR-DB) (0.5 tcyc-40)ns.min (0.5 tcyc-10)ns.min Measuring conditions : VCC = 5 V Input timing voltage : VIL = 0.8 V, VIH = 2.0 V Output timing voltage : VOL = 0.4 V, VOH = 2.4 V Figure 5.15 Timing Diagram (3) Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 63 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 5. Electric Characteristics (Normal-ver.) Memory Expansion Mode and Microprocessor Mode (For 1-wait setting and external area access) Read timing BCLK td(BCLK-CS) 25ns.max VCC = 5 V th(BCLK-CS) 4ns.min CSi tcyc td(BCLK-AD) 25ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min th(RD-AD) 0ns.min ALE td(BCLK-RD) 25ns.max th(BCLK-RD) 0ns.min RD tac2(RD-DB) (1.5 tcyc-45)ns.max DBi Hi-Z th(RD-DB) tSU(DB-RD) 40ns.min 0ns.min Write timing BCLK td(BCLK-CS) 25ns.max th(BCLK-CS) 4ns.min CSi tcyc td(BCLK-AD) 25ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min th(WR-AD) (0.5 tcyc-10)ns.min ALE td(BCLK-WR) 25ns.max th(BCLK-WR) 0ns.min WR,WRL, WRH td(BCLK-DB) 40ns.max Hi-Z th(BCLK-DB) 4ns.min DBi td(DB-WR) 1 tcyc = f(BCLK) (0.5 tcyc-40)ns.min th(WR-DB) (0.5 tcyc-10)ns.min Measuring conditions : VCC = 5 V Input timing voltage : VIL = 0.8 V, VIH = 2.0 V Output timing voltage : VOL = 0.4 V, VOH = 2.4 V Figure 5.16 Timing Diagram (4) Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 64 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 5. Electric Characteristics (Normal-ver.) Memory Expansion Mode and Microprocessor Mode (For 2-wait setting and external area access) Read timing tcyc VCC = 5 V BCLK td(BCLK-CS) 25ns.max th(BCLK-CS) 4ns.min CSi td(BCLK-AD) 25ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min th(RD-AD) 0ns.min ALE td(BCLK-RD) 25ns.max th(BCLK-RD) 0ns.min RD tac2(RD-DB) (2.5 tcyc-45)ns.max DBi Hi-Z tSU(DB-RD) 40ns.min th(RD-DB) 0ns.min Write timing tcyc BCLK td(BCLK-CS) 25ns.max th(BCLK-CS) 4ns.min CSi td(BCLK-AD) 25ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 25ns.max th(WR-AD) th(BCLK-ALE) -4ns.min (0.5 tcyc-10)ns.min ALE td(BCLK-WR) 25ns.max th(BCLK-WR) 0ns.min WR, WRL WRH td(BCLK-DB) 40ns.max th(BCLK-DB) 4ns.min DBi Hi-Z td(DB-WR) (1.5 tcyc-40)ns.min th(WR-DB) (0.5 tcyc-10)ns.min tcyc = 1 f(BCLK) Measuring conditions : VCC = 5 V Input timing voltage : VIL = 0.8 V, VIH = 2.0 V Output timing voltage : VOL = 0.4 V, VOH = 2.4 V Figure 5.17 Timing Diagram (5) Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 65 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 5. Electric Characteristics (Normal-ver.) Memory Expansion Mode and Microprocessor Mode (For 3-wait setting and external area access) Read timing tcyc VCC = 5 V BCLK td(BCLK-CS) 25ns.max th(BCLK-CS) 4ns.min CSi td(BCLK-AD) 25ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min th(RD-AD) 0ns.min ALE td(BCLK-RD) 25ns.max th(BCLK-RD) 0ns.min RD tac2(RD-DB) (3.5 tcyc-45)ns.max DBi Hi-Z tSU(DB-RD) 40ns.min th(RD-DB) 0ns.min Write timing tcyc BCLK td(BCLK-CS) 25ns.max th(BCLK-CS) 4ns.min CSi td(BCLK-AD) 25ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min th(WR-AD) (0.5 tcyc-10)ns.min ALE td(BCLK-WR) 25ns.max th(BCLK-WR) 0ns.min WR, WRL WRH td(BCLK-DB) 40ns.max th(BCLK-DB) 4ns.min DBi Hi-Z td(DB-WR) (2.5 tcyc-40)ns.min th(WR-DB) (0.5 tcyc-10)ns.min 1 tcyc = f(BCLK) Measuring conditions : VCC = 5 V Input timing voltage : VIL = 0.8 V, VIH = 2.0 V Output timing voltage : VOL = 0.4 V, VOH = 2.4 V Figure 5.18 Timing Diagram (6) Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 66 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 5. Electric Characteristics (Normal-ver.) Memory Expansion Mode and Microprocessor Mode (For 1- or 2-wait setting, external area access and multiplexed bus selection) Read timing BCLK td(BCLK-CS) 25ns.max tcyc (0.5 tcyc-10)ns.min VCC = 5 V th(RD-CS) th(BCLK-CS) 4ns.min CSi td(AD-ALE) (0.5 tcyc-25)ns.min (0.5 tcyc-15)ns.min th(ALE-AD) ADi /DBi Address tdZ(RD-AD) 8ns.max Data input tac3(RD-DB) tSU(DB-RD) 40ns.min Address th(RD-DB) 0ns.min (1.5 tcyc-45)ns.max td(AD-RD) td(BCLK-AD) 25ns.max 0ns.min th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min th(RD-AD) (0.5 tcyc-10)ns.min ALE td(BCLK-RD) 25ns.max th(BCLK-RD) 0ns.min RD Write timing BCLK td(BCLK-CS) 25ns.max tcyc (0.5 tcyc-10)ns.min th(WR-CS) th(BCLK-CS) 4ns.min CSi td(BCLK-DB) 40ns.max th(BCLK-DB) 4ns.min ADi /DBi td(AD-ALE) Address Data output td(DB-WR) (1.5 tcyc-40)ns.min Address th(WR-DB) (0.5 tcyc-10)ns.min (0.5 tcyc-25)ns.min td(BCLK-AD) 25ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min td(AD-WR) 0ns.min th(WR-AD) (0.5 tcyc-10)ns.min ALE td(BCLK-WR) 25ns.max th(BCLK-WR) 0ns.min WR,WRL, WRH 1 f(BCLK) tcyc = Measuring conditions : VCC = 5 V Input timing voltage : VIL = 0.8 V, VIH = 2.0 V Output timing voltage : VOL = 0.4 V, VOH = 2.4 V Figure 5.19 Timing Diagram (7) Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 67 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 5. Electric Characteristics (Normal-ver.) Memory Expansion Mode and Microprocessor Mode (For 3-wait setting, external area access and multiplexed bus selection) Read timing tcyc VCC = 5 V BCLK td(BCLK-CS) 25ns.max (0.5 tcyc-10)ns.min th(RD-CS) th(BCLK-CS) 4ns.min CSi td(AD-ALE) (0.5 tcyc-25)ns.min ADi /DBi ADi BHE (no multiplex) 25ns.max (0.5 tcyc-15)ns.min th(ALE-AD) Address td(BCLK-AD) tdZ(RD-AD) td(AD-RD) 0ns.min 8ns.max Data input th(RD-DB) tac3(RD-DB) (2.5 tcyc-45)ns.max tSU(DB-RD) 40ns.min 0ns.min th(BCLK-AD) 4ns.min td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min th(RD-AD) (0.5 tcyc-10)ns.min ALE td(BCLK-RD) 25ns.max th(BCLK-RD) 0ns.min RD Write timing tcyc BCLK td(BCLK-CS) 25ns.max (0.5 tcyc-10)ns.min th(WR-CS) th(BCLK-CS) 4ns.min CSi td(BCLK-DB) 40ns.max th(BCLK-DB) 4ns.min ADi /DBi td(AD-ALE) Address Data output td(DB-WR) (2.5 tcyc-40)ns.min (0.5 tcyc-25)ns.min th(WR-DB) (0.5 tcyc-10)ns.min td(BCLK-AD) 25ns.max th(BCLK-AD) 4ns.min ADi BHE (no multiplex) td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min th(WR-AD) td(AD-WR) (0.5 tcyc-10)ns.min 0ns.min ALE td(BCLK-WR) WR, WRL WRH tcyc = 1 f(BCLK) 25ns.max th(BCLK-WR) 0ns.min Measuring conditions : VCC = 5 V Input timing voltage : VIL = 0.8 V, VIH = 2.0 V Output timing voltage : VOL = 0.4 V, VOH = 2.4 V Figure 5.20 Timing Diagram (8) Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 68 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) Table 5.51 Electrical Characteristics Symbol VOH HIGH output voltage (1) 5. Electric Characteristics (Normal-ver.) VCC = 3.3 V Unit V Standard Parameter Measuring Condition Min. Typ. Max. P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, IOH = -1 mA VCC VCC-0.5 P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7 VOH HIGH output voltage HIGH output voltage XOUT HIGHPOWER LOWPOWER IOH = -0.1 mA IOH = -50 A With no load applied With no load applied VCC-0.5 VCC-0.5 2.5 1.6 VCC VCC V V XCOUT HIGHPOWER LOWPOWER P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 XOUT HIGHPOWER LOWPOWER XCOUT HIGHPOWER LOWPOWER _________ _______ VOL LOW output voltage P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, IOL = 1 mA 0.5 V VOL LOW output voltage LOW output voltage IOL = 0.1 mA IOL = 50 A With no load applied With no load applied 0.2 _________ 0.5 0.5 0 0 0.8 V V V VT+-VT- Hysteresis HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN, ________ ________ _______ _____________ _________ INT0 to INT5, NMI, ADTRG, CTS0 to CTS2, SCL0 to SCL2, SDA0 to SDA2, CLK0 to CLK3, _____ _____ TA0OUT to TA4OUT, KI0 to KI3, RXD0 to RXD2, SIN3 VT+-VT- Hysteresis IIH HIGH input current _____________ RESET P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, VI = 3.3 V P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, ____________ 0.2 1.8 4.0 V A XIN, RESET, CNVSS, BYTE IIL LOW input current P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, VI = 0 V P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, ____________ -4.0 A XIN, RESET, CNVSS, BYTE RPULLUP Pull-up resistance P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, VI = 0 V P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7, RfXIN RfXCIN P10_0 to P10_7 Feedback resistance XIN Feedback resistance XCIN RAM retention voltage 3.0 25 M 50 100 500 k M At stop mode VRAM V 2.0 NOTES: 1. Referenced to VCC = 3.0 to 3.6 V, VSS = 0 V at Topr = -40 to 85C, f(BCLK) = 24 MHz unless otherwise specified. Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 69 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 5. Electric Characteristics (Normal-ver.) Timing Requirements VCC (Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = -40 to 85C unless otherwise specified) Table 5.52 External Clock Input (XIN Input) Symbol tC tw(H) tw(L) tr tf External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock rise time External clock fall time Parameter Standard Min. Max. 62.5 25 25 15 15 = 3.3 V Unit ns ns ns ns ns Table 5.53 Memory Expansion Mode and Microprocessor Mode Symbol tac1(RD-DB) tac2(RD-DB) tac3(RD-DB) tsu(DB-RD) tsu(RDY-BCLK) Parameter Data input access time (for setting with no wait) Data input access time (for setting with wait) Data input access time (when accessing multiplexed bus area) Data input setup time ________ Standard Unit Min. Max. (NOTE 1) ns (NOTE 2) ns (NOTE 3) 50 40 50 0 0 0 ns ns ns ns ns ns ns RDY input setup time __________ tsu(HOLD-BCLK) HOLD input setup time th(RD-DB) Data input hold time ________ th(BCLK-RDY) RDY input hold time __________ th(BCLK-HOLD) HOLD input hold time NOTES: 1. Calculated according to the BCLK frequency as follows: 0.5 10 - 60 [ns] f(BCLK) 9 2. Calculated according to the BCLK frequency as follows: (n -0.5) 10 f(BCLK) 9 - 60 [ns] n is "2" for 1-wait setting, "3" for 2-wait setting and "4" for 3-wait setting. 3. Calculated according to the BCLK frequency as follows: (n -0.5) 109 - 60 [ns] f(BCLK) n is "2" for 2-wait setting, "3" for 3-wait setting. Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 70 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 5. Electric Characteristics (Normal-ver.) Timing Requirements VCC (Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = -40 to 85C unless otherwise specified) Table 5.54 Timer A Input (Counter Input in Event Counter Mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. Max. 150 60 60 = 3.3 V Unit ns ns ns Table 5.55 Timer A Input (Gating Input in Timer Mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. Max. 600 300 300 Unit ns ns ns Table 5.56 Timer A Input (External Trigger Input in One-shot Timer Mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. Max. 300 150 150 Unit ns ns ns Table 5.57 Timer A Input (External Trigger Input in Pulse Width Modulation Mode) Symbol tw(TAH) tw(TAL) TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. Max. 150 150 Unit ns ns Table 5.58 Timer A Input (Counter Increment/decrement Input in Event Counter Mode) Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) TAiOUT input cycle time TAiOUT input HIGH pulse width TAiOUT input LOW pulse width TAiOUT input setup time TAiOUT input hold time Parameter Standard Min. Max. 3000 1500 1500 600 600 Unit ns ns ns ns ns Table 5.59 Timer A Input (Two-phase Pulse Input in Event Counter Mode) Symbol TAiIN input cycle time tsu(TAIN-TAOUT) TAiOUT input setup time tsu(TAOUT-TAIN) TAiIN input setup time tc(TA) Parameter Standard Max. Min. 2 500 500 Unit s ns ns Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 71 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 5. Electric Characteristics (Normal-ver.) Timing Requirements VCC (Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = -40 to 85C unless otherwise specified) Table 5.60 Timer B Input (Counter Input in Event Counter Mode) Symbol Parameter TBiIN input cycle time (counted on one edge) TBiIN input HIGH pulse width (counted on one edge) TBiIN input LOW pulse width (counted on one edge) TBiIN input cycle time (counted on both edges) TBiIN input HIGH pulse width (counted on both edges) TBiIN input LOW pulse width (counted on both edges) Standard Min. Max. 150 60 60 300 120 120 = 3.3 V Unit ns ns ns ns ns ns tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Table 5.61 Timer B Input (Pulse Period Measurement Mode) Symbol Parameter TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width Standard Min. Max. 600 300 300 Unit ns ns ns tc(TB) tw(TBH) tw(TBL) Table 5.62 Timer B Input (Pulse Width Measurement Mode) Symbol Parameter TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width Standard Min. Max. 600 300 300 Unit ns ns ns tc(TB) tw(TBH) tw(TBL) Table 5.63 A/D Trigger Input Symbol Parameter _____________ tC(AD) tw(ADL) ADTRG input cycle time (trigger able minimum) _____________ Standard Min. Max. 1500 200 Unit ns ns ADTRG input LOW pulse width Table 5.64 Serial Interface Symbol Parameter CLKi input cycle time CLKi input HIGH pulse width CLKi input LOW pulse width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time _______ tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) Standard Min. Max. 300 150 150 160 0 100 90 Unit ns ns ns ns ns ns ns Table 5.65 External Interrupt INTi Input Symbol Parameter _______ tw(INH) tw(INL) INTi input HIGH pulse width _______ INTi input LOW pulse width Standard Min. Max. 380 380 Unit ns ns Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 72 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 5. Electric Characteristics (Normal-ver.) Switching Characteristics VCC (Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = -40 to 85 C unless otherwise specified) Table 5.66 Memory Expansion Mode and Microprocessor Mode (for setting with no wait) Symbol Parameter Address output delay time Address output hold time (in relation to BCLK) Address output hold time (in relation to RD) Address output hold time (in relation to WR) Chip select output delay time Chip select output hold time (in relation to BCLK) ALE signal output delay time ALE signal output hold time RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (in relation to BCLK) Data output hold time (in relation to BCLK) Data output delay time (in relation to WR) Data output hold time (in relation to WR) __________ = 3.3 V Measuring Condition Figure 5.21 td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) td(BCLK-HLDA) Standard Min. Max. 30 4 0 (NOTE 1) 30 4 25 -4 30 0 30 0 40 4 (NOTE 2) (NOTE 1) 40 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (3) (3) HLDA output delay time NOTES: 1. Calculated according to the BCLK frequency as follows: 0.5 10 - 10 [ns] f(BCLK) 9 2. Calculated according to the BCLK frequency as follows: 0.5 10 - 40 [ns] f(BCLK) 9 f(BCLK) is 12.5 MHz or less. 3. This standard value shows the timing when the output is off, and does not show hold time of data bus. Hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = - CR ln (1 - VOL / VCC) by a circuit of the right figure. For example, when VOL = 0.2 VCC, C = 30 pF, R =1 k, hold time of output "L" level is t = - 30 pF 1 k ln (1 - 0.2 VCC / VCC) = 6.7 ns. R DBi C P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 30 pF Figure 5.21 Port P0 to P10 Measurement Circuit Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 73 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 5. Electric Characteristics (Normal-ver.) Switching Characteristics VCC (Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = -40 to 85 C unless otherwise specified) = 3.3 V Table 5.67 Memory Expansion Mode and Microprocessor Mode (for 1- to 3-wait setting and external area access) Symbol Parameter Address output delay time Address output hold time (in relation to BCLK) Address output hold time (in relation to RD) Address output hold time (in relation to WR) Chip select output delay time Chip select output hold time (in relation to BCLK) ALE signal output delay time ALE signal output hold time RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (in relation to BCLK) Data output hold time (in relation to BCLK) Data output delay time (in relation to WR) Data output hold time (in relation to WR) __________ Measuring Condition Figure 5.21 td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) td(BCLK-HLDA) Standard Min. Max. 30 4 0 (NOTE 1) 30 4 25 -4 30 0 30 0 40 4 (NOTE 2) (NOTE 1) 40 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (3) (3) HLDA output delay time NOTES: 1. Calculated according to the BCLK frequency as follows: 0.5 10 - 10 [ns] f(BCLK) 9 2. Calculated according to the BCLK frequency as follows: (n - 0.5) 10 - 40 [ns] f(BCLK) 9 n is "1" for 1-wait setting, "2" for 2-wait setting and "3" for 3-wait setting. When n = 1, f(BCLK) is 12.5 MHz or less. 3. This standard value shows the timing when the output is off, and does not show hold time of data bus. Hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = - CR ln (1 - VOL / VCC) by a circuit of the right figure. For example, when VOL = 0.2 VCC, C = 30 pF, R =1 k, hold time of output "L" level is t = - 30 pF 1 k ln (1 - 0.2 VCC / VCC) = 6.7 ns. R DBi C Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 74 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 5. Electric Characteristics (Normal-ver.) Switching Characteristics VCC (Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = -40 to 85 C unless otherwise specified) Table 5.68 Memory Expansion Mode and Microprocessor Mode (for 2- to 3-wait setting, external area access and multiplexed bus selection) Symbol Parameter Address output delay time Address output hold time (in relation to BCLK) Address output hold time (in relation to RD) Address output hold time (in relation to WR) Chip select output delay time Chip select output hold time (in relation to BCLK) Chip select output hold time (in relation to RD) Chip select output hold time (in relation to WR) RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (in relation to BCLK) Data output hold time (in relation to BCLK) Data output delay time (in relation to WR) Data output hold time (in relation to WR) __________ = 3.3 V Measuring Condition Figure 5.21 td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) th(RD-CS) th(WR-CS) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) td(BCLK-HLDA) Standard Min. Max. 50 4 (NOTE 1) (NOTE 1) 50 4 (NOTE 1) (NOTE 1) 40 0 40 0 50 4 (NOTE 2) (NOTE 1) 40 25 -4 (NOTE 3) (NOTE 4) 0 0 8 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns HLDA output delay time ALE signal output delay time (in relation to BCLK) ALE signal output hold time (in relation to BCLK) ALE signal output delay time (in relation to Address) ALE signal output hold time (in relation to Address) RD signal output delay from the end of Address WR signal output delay from the end of Address Address output floating start time td(BCLK-ALE) th(BCLK-ALE) td(AD-ALE) th(ALE-AD) td(AD-RD) td(AD-WR) tdZ(RD-AD) NOTES: 1. Calculated according to the BCLK frequency as follows: 0.5 109 - 10 [ns] f(BCLK) 2. Calculated according to the BCLK frequency as follows: (n -0.5) 10 f(BCLK) 9 - 50 [ns] n is "2" for 2-wait setting, "3" for 3-wait setting. 3. Calculated according to the BCLK frequency as follows: 0.5 10 - 40 [ns] f(BCLK) 9 4. Calculated according to the BCLK frequency as follows: 0.5 109 - 15 [ns] f(BCLK) Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 75 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 5. Electric Characteristics (Normal-ver.) VCC = 3.3 V XIN input tr tw(H) tr tc tc(TA) tw(TAH) TAiIN input tw(TAL) tc(UP) tw(UPH) TAiOUT input tw(UPL) TAiOUT input (Up/down input) tw(L) During event counter mode TAiIN input (When count on falling edge is selected) th(TIN--UP) tsu(UP--TIN) TAiIN input (When count on rising edge is selected) Two-phase pulse input in event counter mode tC(TA) TAiIN input tsu(TAIN--TAOUT) TAiOUT input tsu(TAOUT--TAIN) tc(TB) tw(TBH) TBiIN input tw(TBL) tc(AD) tw(ADL) ADTRG input tc(CK) tw(CKH) CLKi tw(CKL) TXDi td(C--Q) RXDi tw(INL) INTi input tw(INH) tsu(D--C) th(C--D) th(C--Q) tsu(TAIN--TAOUT) tsu(TAOUT--TAIN) Figure 5.22 Timing Diagram (1) Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 76 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 5. Electric Characteristics (Normal-ver.) Memory Expansion Mode and Microprocessor Mode (Effective for setting with wait) VCC = 3.3 V BCLK RD (Separate bus) WR, WRL, WRH (Separate bus) RD (Multiplexed bus) WR, WRL, WRH (Multiplexed bus) RDY input tsu(RDY-BCLK) th(BCLK-RDY) (Common to setting with wait and setting without wait) BCLK tsu(HOLD-BCLK) HOLD input th(BCLK-HOLD) HLDA output P0, P1, P2, P3, P4, P5_0 to P5_2 (1) td(BCLK-HLDA) td(BCLK-HLDA) Hi-Z NOTE: 1. The above pins are set to high-impedance regardless of the input level of the BYTE pin, the PM06 bit in the PM0 register, and the PM11 bit in the PM1 register. Measuring conditions : VCC = 3.3 V Input timing voltage : Determined with VIL = 0.6 V, VIH = 2.7 V Output timing voltage: Determined with VOL = 1.65 V, VOH = 1.65 V Figure 5.23 Timing Diagram (2) Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 77 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 5. Electric Characteristics (Normal-ver.) Memory Expansion Mode and Microprocessor Mode (For setting with no wait) Read timing BCLK td(BCLK-CS) 30ns.max VCC = 3.3 V th(BCLK-CS) 4ns.min CSi tcyc td(BCLK-AD) 30ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 30ns.max th(BCLK-ALE) -4ns.min th(RD-AD) 0ns.min ALE td(BCLK-RD) 30ns.max th(BCLK-RD) 0ns.min RD tac1(RD-DB) (0.5 tcyc-60)ns.max Hi-Z DBi tSU(DB-RD) 50ns.min th(RD-DB) 0ns.min Write timing BCLK td(BCLK-CS) 30ns.max th(BCLK-CS) 4ns.min CSi tcyc td(BCLK-AD) 30ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 30ns.max th(BCLK-ALE) -4ns.min th(WR-AD) (0.5 tcyc-10)ns.min ALE td(BCLK-WR) 30ns.max th(BCLK-WR) 0ns.min WR,WRL, WRH td(BCLK-DB) 40ns.max Hi-Z th(BCLK-DB) 4ns.min DBi td(DB-WR) 1 tcyc = f(BCLK) th(WR-DB) (0.5 tcyc-40)ns.min (0.5 tcyc-10)ns.min Measuring conditions : VCC = 3.3 V Input timing voltage : VIL = 0.6 V, VIH = 2.7 V Output timing voltage : VOL = 1.65 V, VOH = 1.65 V Figure 5.24 Timing Diagram (3) Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 78 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 5. Electric Characteristics (Normal-ver.) Memory Expansion Mode and Microprocessor Mode (For 1-wait setting and external area access) Read timing BCLK td(BCLK-CS) 30ns.max VCC = 3.3 V th(BCLK-CS) 4ns.min CSi tcyc td(BCLK-AD) 30ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 30ns.max th(BCLK-ALE) -4ns.min th(RD-AD) 0ns.min ALE td(BCLK-RD) 30ns.max th(BCLK-RD) 0ns.min RD tac2(RD-DB) (1.5 tcyc-60)ns.max DBi Hi-Z th(RD-DB) tSU(DB-RD) 50ns.min 0ns.min Write timing BCLK td(BCLK-CS) 30ns.max th(BCLK-CS) 4ns.min CSi tcyc td(BCLK-AD) 30ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 30ns.max th(BCLK-ALE) -4ns.min th(WR-AD) (0.5 tcyc-10)ns.min ALE td(BCLK-WR) 30ns.max th(BCLK-WR) 0ns.min WR,WRL, WRH td(BCLK-DB) 40ns.max Hi-Z th(BCLK-DB) 4ns.min DBi td(DB-WR) 1 tcyc = f(BCLK) (0.5 tcyc-40)ns.min th(WR-DB) (0.5 tcyc-10)ns.min Measuring conditions : VCC = 3.3 V Input timing voltage : VIL = 0.6 V, VIH = 2.7 V Output timing voltage : VOL = 1.65 V, VOH = 1.65 V Figure 5.25 Timing Diagram (4) Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 79 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 5. Electric Characteristics (Normal-ver.) Memory Expansion Mode and Microprocessor Mode (For 2-wait setting and external area access) Read timing tcyc VCC = 3.3 V BCLK td(BCLK-CS) 30ns.max th(BCLK-CS) 4ns.min CSi td(BCLK-AD) 30ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 30ns.max th(BCLK-ALE) -4ns.min th(RD-AD) 0ns.min ALE td(BCLK-RD) 30ns.max th(BCLK-RD) 0ns.min RD tac2(RD-DB) (2.5 tcyc-60)ns.max DBi Hi-Z tSU(DB-RD) 50ns.min th(RD-DB) 0ns.min Write timing tcyc BCLK td(BCLK-CS) 30ns.max th(BCLK-CS) 4ns.min CSi td(BCLK-AD) 30ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 30ns.max th(WR-AD) th(BCLK-ALE) -4ns.min (0.5 tcyc-10)ns.min ALE td(BCLK-WR) 30ns.max th(BCLK-WR) 0ns.min WR, WRL WRH td(BCLK-DB) 40ns.max th(BCLK-DB) 4ns.min DBi Hi-Z td(DB-WR) (1.5 tcyc-40)ns.min th(WR-DB) (0.5 tcyc-10)ns.min 1 tcyc = f(BCLK) Measuring conditions : VCC = 3.3 V Input timing voltage : VIL = 0.6 V, VIH = 2.7 V Output timing voltage : VOL = 1.65 V, VOH = 1.65 V Figure 5.26 Timing Diagram (5) Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 80 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 5. Electric Characteristics (Normal-ver.) Memory Expansion Mode and Microprocessor Mode (For 3-wait setting and external area access) Read timing tcyc VCC = 3.3 V BCLK td(BCLK-CS) 30ns.max th(BCLK-CS) 4ns.min CSi td(BCLK-AD) 30ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 30ns.max th(BCLK-ALE) -4ns.min th(RD-AD) 0ns.min ALE td(BCLK-RD) 30ns.max th(BCLK-RD) 0ns.min RD tac2(RD-DB) (3.5 tcyc-60)ns.max DBi Hi-Z tSU(DB-RD) 50ns.min th(RD-DB) 0ns.min Write timing tcyc BCLK td(BCLK-CS) 30ns.max th(BCLK-CS) 4ns.min CSi td(BCLK-AD) 30ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 30ns.max th(BCLK-ALE) -4ns.min th(WR-AD) (0.5 tcyc-10)ns.min ALE td(BCLK-WR) 30ns.max th(BCLK-WR) 0ns.min WR, WRL WRH td(BCLK-DB) 40ns.max th(BCLK-DB) 4ns.min DBi Hi-Z td(DB-WR) (2.5 tcyc-40)ns.min th(WR-DB) (0.5 tcyc-10)ns.min 1 tcyc = f(BCLK) Measuring conditions : VCC = 3.3 V Input timing voltage : VIL = 0.6 V, VIH = 2.7 V Output timing voltage : VOL = 1.65 V, VOH = 1.65 V Figure 5.27 Timing Diagram (6) Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 81 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 5. Electric Characteristics (Normal-ver.) Memory Expansion Mode and Microprocessor Mode (For 2-wait setting, external area access and multiplexed bus selection) Read timing BCLK td(BCLK-CS) 40ns.max tcyc (0.5 tcyc-10)ns.min VCC = 3.3 V th(RD-CS) th(BCLK-CS) 4ns.min CSi td(AD-ALE) (0.5 tcyc-40)ns.min (0.5 tcyc-15)ns.min th(ALE-AD) ADi /DBi Address tdZ(RD-AD) 8ns.max Data input tac3(RD-DB) tSU(DB-RD) 50ns.min Address th(RD-DB) 0ns.min (1.5 tcyc-60)ns.max td(AD-RD) td(BCLK-AD) 40ns.max 0ns.min th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 40ns.max th(BCLK-ALE) -4ns.min th(RD-AD) (0.5 tcyc-10)ns.min ALE td(BCLK-RD) 40ns.max th(BCLK-RD) 0ns.min RD Write timing BCLK td(BCLK-CS) 40ns.max tcyc (0.5 tcyc-10)ns.min th(WR-CS) th(BCLK-CS) 4ns.min CSi td(BCLK-DB) 50ns.max th(BCLK-DB) 4ns.min ADi /DBi td(AD-ALE) Address Data output td(DB-WR) (1.5 tcyc-50)ns.min Address th(WR-DB) (0.5 tcyc-10)ns.min (0.5 tcyc-40)ns.min td(BCLK-AD) 40ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 40ns.max th(BCLK-ALE) -4ns.min td(AD-WR) 0ns.min th(WR-AD) (0.5 tcyc-10)ns.min ALE td(BCLK-WR) 40ns.max th(BCLK-WR) 0ns.min WR,WRL, WRH 1 f(BCLK) tcyc = Measuring conditions : VCC = 3.3 V Input timing voltage : VIL = 0.6 V, VIH = 2.7 V Output timing voltage : VOL = 1.65 V, VOH = 1.65 V Figure 5.28 Timing Diagram (7) Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 82 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) 5. Electric Characteristics (Normal-ver.) Memory Expansion Mode and Microprocessor Mode (For 3-wait setting, external area access and multiplexed bus selection) Read timing tcyc VCC = 3.3 V BCLK td(BCLK-CS) 40ns.max (0.5 tcyc-10)ns.min th(RD-CS) th(BCLK-CS) 6ns.min CSi td(AD-ALE) (0.5 tcyc-40)ns.min ADi /DBi ADi BHE (no multiplex) 40ns.max (0.5 tcyc-15)ns.min th(ALE-AD) Address td(BCLK-AD) tdZ(RD-AD) td(AD-RD) 0ns.min 8ns.max Data input th(RD-DB) tac3(RD-DB) (2.5 tcyc-60)ns.max tSU(DB-RD) 50ns.min 0ns.min th(BCLK-AD) 4ns.min td(BCLK-ALE) 40ns.max th(BCLK-ALE) -4ns.min th(RD-AD) (0.5 tcyc-10)ns.min ALE td(BCLK-RD) 40ns.max th(BCLK-RD) 0ns.min RD Write timing tcyc BCLK td(BCLK-CS) 40ns.max (0.5 tcyc-10)ns.min th(WR-CS) th(BCLK-CS) 4ns.min CSi td(BCLK-DB) 50ns.max th(BCLK-DB) 4ns.min ADi /DBi td(AD-ALE) Address Data output td(DB-WR) (2.5 tcyc-50)ns.min (0.5 tcyc-40)ns.min th(WR-DB) (0.5 tcyc-10)ns.min td(BCLK-AD) 40ns.max th(BCLK-AD) 4ns.min ADi BHE (no multiplex) td(BCLK-ALE) 40ns.max th(BCLK-ALE) -4ns.min th(WR-AD) td(AD-WR) (0.5 tcyc-10)ns.min 0ns.min ALE td(BCLK-WR) WR, WRL WRH tcyc = 1 f(BCLK) 40ns.max th(BCLK-WR) 0ns.min Measuring conditions : VCC = 3.3 V Input timing voltage : VIL = 0.6 V, VIH = 2.7 V Output timing voltage : VOL = 1.65 V, VOH = 1.65 V Figure 5.29 Timing Diagram (8) Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 83 of 84 Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6N5) Appendix 1. Package Dimensions Appendix 1. Package Dimensions JEITA Package Code P-QFP100-14x20-0.65 RENESAS Code PRQP0100JB-A Previous Code 100P6S-A MASS[Typ.] 1.6g HD *1 80 D 51 81 50 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. *2 HE E ZE Reference Symbol Dimension in Millimeters 100 31 1 ZD Index mark 30 F c L e y *3 bp Detail F D E A2 HD HE A A1 bp c e y ZD ZE L Min Nom Max 19.8 20.0 20.2 13.8 14.0 14.2 2.8 22.5 22.8 23.1 16.5 16.8 17.1 3.05 0.1 0.2 0 0.25 0.3 0.4 0.13 0.15 0.2 0 10 0.5 0.65 0.8 0.10 0.575 0.825 0.4 0.6 0.8 A JEITA Package Code P-LQFP100-14x14-0.50 RENESAS Code PLQP0100KB-A Previous Code 100P6Q-A / FP-100U / FP-100UV MASS[Typ.] 0.6g HD *1 D 75 51 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 76 50 bp b1 HE E A1 A2 Reference Symbol *2 Dimension in Millimeters c1 c Terminal cross section 1 Index mark ZD 25 F ZE 100 26 A2 A D E A2 HD HE A A1 bp b1 c c1 c A1 y e *3 bp L L1 Detail F x e x y ZD ZE L L1 Min Nom Max 13.9 14.0 14.1 13.9 14.0 14.1 1.4 15.8 16.0 16.2 15.8 16.0 16.2 1.7 0.05 0.1 0.15 0.15 0.20 0.25 0.18 0.09 0.145 0.20 0.125 0 8 0.5 0.08 0.08 1.0 1.0 0.35 0.5 0.65 1.0 Rev.2.40 Aug 25, 2006 REJ03B0004-0240 page 84 of 84 REVISION HISTORY Rev. Date M16C/6N Group (M16C/6N5) Data Sheet Description Page - - First edition issued Summary Revised edition issued * Words standardizes (on-chip oscillator) * 100P6Q-A (100-pin version) is added. * Revised parts and revised contents are as follows (except for change of a layout and an expressional change). 1. Overview 3rd line: "and LQFP" is added. Table 1.1 Performance outline of M16C/6N Group (M16C/6N5) * Operation Mode is added. * Address Space is added. * Power Consumption is revised. * "LQFP" is added to Package. Table 1.2 Product List is revised. Figure 1.2 Type No., Memory Size, and Package: * "GP: Package 100P6Q-A" is added to Package type. Figure 1.3 Pin Configuration (Top View) (1): "ZP" is added. Figure 1.4 Pin Configuration (Top View) (2) is added. (100P6Q-A) Table 1.4 Pin Description (2): "ZP" is added to Timer A. 3. Memory * 5th to 6th lines: The description about the flash memory version (block A) is added. Figure 3.1 Memory Map * Interenal ROM (data area) is added. * NOTES 3, 4 are added and NOTE 5 is revised. Table 4.1 SFR Information (1) * The value of After Reset in PM1 register is revised. * The value of After Reset in CM2 register is revised. Table 4.7 SFR Information (7) * The value of After Reset in FMR0 register is revised. Table 4.11 SFR Information (11) * The value of After Reset in U0C1 register is revised. * The value of After Reset in U1C1 register is revised. * NOTE 1 is added. Table 4.12 SFR Information (12) * The value of After Reset in DA0, DA1 registers are revised. Table 5.1 Absolute Maximum Ratings * "Flash Program Erase" in Operating Ambient Temperature is added. Table 5.3 Recommended Operating Conditions (2) * Parameters of Power Supply Ripple are added. * NOTE 4 is revised. Figure 5.1 Timing of Voltage Fluctuation is added. Table 5.4 Electrical Characteristics (1): Hysteresis * "CLK4" is revised to ____________ and "TA2OUT" is revised to "TA0OUT". "CLK3", * Max. of Standard in RESET is revised from "2.2" to "2.5". * XIN is added. 1.00 Jun. 30, 2003 2.00 Nov. 10, 2004 1 2 4 5 6 8 12 13 19 23 24 25 27 28 A-1 REVISION HISTORY Rev. Date M16C/6N Group (M16C/6N5) Data Sheet Description Page 30 31 32 34 35 Summary Table 5.6 A/D Conversion Characteristics: "Tolerance Level Impedance" is added. Table 5.8 Power Supply Circuit Timing Characteristics: "td(M-L)" is deleted. Figure 5.2 Power Supply Circuit Timing Diagram is added. Table 5.10 Memory Expansion Mode and Microprocessor Mode: "td(BCLK-HLDA)" is deleted. Table 5.21 Serial I/O: Min. of standard in tsu(D-C) is revised from "30" to "70". Table 5.23 Memory Expansion Mode and Microprocessor Mode (for setting with no wait) * Max. of Standard in td(BCLK-ALE) is revised from "25" to "15". * td(BCLK-HLDA) is added. 2.00 Nov. 10, 2004 36 Table 5.24 Memory Expansion Mode and Microprocessor Mode (for 1- to 3-wait setting and external area access) * Max. of Standard in td(BCLK-ALE) is revised from "25" to "15". * td(BCLK-HLDA) is added. 37 Table 5.25 Memory Expansion Mode and Microprocessor Mode (for 2- to 3-wait setting, external area access and multiplexed bus selection) * td(BCLK-HLDA) is added. * Max. of Standard in td(BCLK-ALE) is revised from "25" to "15". 38 40, 41 42, 43 45 46 2.10 Jun. 24, 2005 - Figure 5.4 Timing Diagram (1): "XIN input" is added. Figures 5.6 and 5.7 Timing Diagram (3) (4): "DB" in Read timing is revised to "DBi". Figures 5.8 and 5.9 Timing Diagram (5) (6): "DB" in Write timing is revised to "DBi". Figure 5.11 Timing Diagram (8) * "ADi/DB" in Read/Write timing is revised to "ADi/DBi". Appendix 1. Package Dimensions: 100P6Q-A is added. Revised edition issued * The contents of product are revised. (Normal-ver. is added.) * Revised parts and revised contents are as follows (except for expressional change). 2 4 Table 1.1 Performance outline of M16C/6N Group (M16C/6N5) * Performance outline of Normal-ver. is added. Table 1.2 Product List is revised. (Normal-ver. is added.) Figure 1.2 Type No., Memory Size, and Package: * "(no): Normal-ver." is added to Characteristics. 19 28 29 30 2.40 Aug. 25, 2006 - Figure 4.7 SFR Information (7): NOTE 1 is revised. Table 5.4 Electrical Characteristics (1) * Measuring Condition of VOL is revised from "LOL = -200A" to "LOL = 200A". Table 5.5 Electrical Characteristics (2): Mask ROM (5th item) * "f(XCIN)" is changed to "(f(BCLK)). Table 5.6 A/D Conversion Characteristics: "Tolerance Level Impedance" is deleted. Revised edition issued * Electric Characteristics of Normal-ver. is added. * Revised parts and revised contents are as follows (except for expressional change). 1 4 1.1 Applications: Comment of Normal-ver. is added. Table 1.2 Product Information * Status of development is revised and NOTES 1 and 2 are added. A-2 REVISION HISTORY Rev. Date M16C/6N Group (M16C/6N5) Data Sheet Description Page 7, 8 9 22 Table 1.5 Pin Functions (1) Summary Tables 1.3 and 1.4 List of Pin Names (1)(2) are added. * 3.0 to 5.5 V (Normal-ver.) is added to Description of Power supply input. Table 4.8 SFR Information (8) * The value of After Reset in IDB0 register is revised. * The value of After Reset in IDB1 register is revised. 2.40 Aug. 25, 2006 29 Table 5.3 Recommended Operating Conditions (2) * Power supply ripple is deleted. (three items) Figure 5.1 Voltage Fluctuation Timing is deleted. 30 48 to 83 Table 5.4 Electrical Characteristics (1): Hysteresis XIN is deleted. 5.2 Electrical Characteristics (Normal-ver.) is added. A-3 Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. 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